Parallel Flow-Sensitive Pointer Analysis by Graph-Rewriting

Precise pointer analysis is a problem of interest to both the compiler and the program verification community. Flow-sensitivity is an important dimension of pointer analysis that affects the precision of the final result computed. Scaling flow-sensitive pointer analysis to millions of lines of code is a major challenge. Recently, staged flow-sensitive pointer analysis has been proposed, which exploits a sparse representation of program code created by staged analysis. In this paper we formulate the staged flow-sensitive pointer analysis as a graph-rewriting problem. Graph-rewriting has already been used for flow-insensitive analysis. However, formulating flow-sensitive pointer analysis as a graph-rewriting problem adds additional challenges due to the nature of flow-sensitivity. We implement our parallel algorithm using Intel Threading Building Blocks and demonstrate considerable scaling (upto 2.6x) for 8 threads on a set of 10 benchmarks. Compared to the sequential implementation of staged flow-sensitive analysis, a single threaded execution of our implementation performs better in 8 of the benchmarks.

Role of surface chemistry in modulating drug release kinetics in titania nanotubes

Surface chemistry and the intrinsic porous architectures of porous substrates play a major role in the design of drug delivery systems. An interesting example is the drug elution characteristic from hydrothermally synthesised titania nanotubes with tunable surface chemistry. The variation in release rates of Ibuprofen (IBU) is largely influenced by the nature of the functional groups on titania nanotubes and pH of suspending medium. To elucidate the extent of interaction between the encapsulated IBU and the functional groups on titania nanotubes, the release profiles have been modelled with an empirical Hill equation. The analysis aided in establishing a probable mechanism for the release of IBU from the titania nanotubes. The study of controlled drug release from TiO2 has wider implication in the context of biomedical engineering. (C) 2014 Elsevier B.V. All rights reserved.

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths

In this paper we present a framework for realizing arbitrary instruction set extensions (IE) that are identified post-silicon. The proposed framework has two components viz., an IE synthesis methodology and the architecture of a reconfigurable data-path for realization of the such IEs. The IE synthesis methodology ensures maximal utilization of resources on the reconfigurable data-path. In this context we present the techniques used to realize IEs for applications that demand high throughput or those that must process data streams. The reconfigurable hardware called HyperCell comprises a reconfigurable execution fabric. The fabric is a collection of interconnected compute units. A typical use case of HyperCell is where it acts as a co-processor with a host and accelerates execution of IEs that are defined post-silicon. We demonstrate the effectiveness of our approach by evaluating the performance of some well-known integer kernels that are realized as IEs on HyperCell. Our methodology for realizing IEs through HyperCells permits overlapping of potentially all memory transactions with computations. We show significant improvement in performance for streaming applications over general purpose processor based solutions, by fully pipelining the data-path. (C) 2014 Elsevier B.V. All rights reserved.

Hybrid and Rogue Kinases Encoded in the Genomes of Model Eukaryotes

The highly modular nature of protein kinases generates diverse functional roles mediated by evolutionary events such as domain recombination, insertion and deletion of domains. Usually domain architecture of a kinase is related to the subfamily to which the kinase catalytic domain belongs. However outlier kinases with unusual domain architectures serve in the expansion of the functional space of the protein kinase family. For example, Src kinases are made-up of SH2 and SH3 domains in addition to the kinase catalytic domain. A kinase which lacks these two domains but retains sequence characteristics within the kinase catalytic domain is an outlier that is likely to have modes of regulation different from classical src kinases. This study defines two types of outlier kinases: hybrids and rogues depending on the nature of domain recombination. Hybrid kinases are those where the catalytic kinase domain belongs to a kinase subfamily but the domain architecture is typical of another kinase subfamily. Rogue kinases are those with kinase catalytic domain characteristic of a kinase subfamily but the domain architecture is typical of neither that subfamily nor any other kinase subfamily. This report provides a consolidated set of such hybrid and rogue kinases gleaned from six eukaryotic genomes-S. cerevisiae, D. melanogaster, C. elegans, M. musculus, T. rubripes and H. sapiens-and discusses their functions. The presence of such kinases necessitates a revisiting of the classification scheme of the protein kinase family using full length sequences apart from classical classification using solely the sequences of kinase catalytic domains. The study of these kinases provides a good insight in engineering signalling pathways for a desired output. Lastly, identification of hybrids and rogues in pathogenic protozoa such as P. falciparum sheds light on possible strategies in host-pathogen interactions.

Hardware Accelerator for 3D Method of Moments based Parasitic Extraction

A Field Programmable Gate Array (FPGA) based hardware accelerator for multi-conductor parasitic capacitance extraction, using Method of Moments (MoM), is presented in this paper. Due to the prohibitive cost of solving a dense algebraic system formed by MoM, linear complexity fast solver algorithms have been developed in the past to expedite the matrix-vector product computation in a Krylov sub-space based iterative solver framework. However, as the number of conductors in a system increases leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products present a time bottleneck, especially for ill-conditioned system matrices. In this work, an FPGA based hardware implementation is proposed to parallelize the iterative matrix solution for multiple RHS vectors in a low-rank compression based fast solver scheme. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple conductors in a Ball Grid Array (BGA) package. Speed-ups up to 13x over equivalent software implementation on an Intel Core i5 processor for dense matrix-vector products and 12x for QR compressed matrix-vector products is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board.

Using formal reasoning on a model of tasks for FreeRTOS

FreeRTOS is an open-source real-time microkernel that has a wide community of users. We present the formal specification of the behaviour of the task part of FreeRTOS that deals with the creation, management, and scheduling of tasks using priority-based preemption. Our model is written in the Z notation, and we verify its consistency using the Z/Eves theorem prover. This includes a precise statement of the preconditions for all API commands. This task model forms the basis for three dimensions of further work: (a) the modelling of the rest of the behaviour of queues, time, mutex, and interrupts in FreeRTOS; (b) refinement of the models to code to produce a verified implementation; and (c) extension of the behaviour of FreeRTOS to multi-core architectures. We propose all three dimensions as benchmark challenge problems for Hoare's Verified Software Initiative.

A Novel and Scalable LED Communication System

We describe our novel LED communication infrastructure and demonstrate its scalability across platforms. Our system achieves 50 kilo bits per second on very simple SoCs and scales to megabits bits per second rates on dual processor based mobile phone platforms.

Typical and atypical domain combinations in human protein kinases: functions, disease causing mutations and conservation in other primates

Ser/Thr and Tyr protein kinases orchestrate many signalling pathways and hence loss in this balance leads to many disease phenotypes. Due to their high abundance, diversity and importance, efforts have been made in the past to classify kinases and annotate their functions at both gross and fine levels. These kinases are conventionally classified into subfamilies based on the sequences of catalytic domains. Usually the domain architecture of a full-length kinase is consistent with the subfamily classification made based on the sequence of kinase domain. Important contributions of modular domains to the overall function of the kinase are well known. Recently occurrence of two kinds of outlier kinases-''Hybrid'' and ``Rogue'' has been reported. These show considerable deviations in their domain architectures from the typical domain architecture known for the classical kinase subfamilies. This article provides an overview of the different subfamilies of human kinases and the role of non-kinase domains in functions and diseases. Importantly this article provides analysis of hybrid and rogue kinases encoded in the human genome and highlights their conservation in closely related primate species. These kinases are examples of elegant rewiring to bring about subtle functional differences compared to canonical variants.

An Implementation of Partitioned Scheduling Scheme for Hard Real-Time Tasks in Multicore Linux with Fair Share for Linux Tasks

The correctness of a hard real-time system depends its ability to meet all its deadlines. Existing real-time systems use either a pure real-time scheduler or a real-time scheduler embedded as a real-time scheduling class in the scheduler of an operating system (OS). Existing implementations of schedulers in multicore systems that support real-time and non-real-time tasks, permit the execution of non-real-time tasks in all the cores with priorities lower than those of real-time tasks, but interrupts and softirqs associated with these non-real-time tasks can execute in any core with priorities higher than those of real-time tasks. As a result, the execution overhead of real-time tasks is quite large in these systems, which, in turn, affects their runtime. In order that the hard real-time tasks can be executed in such systems with minimal interference from other Linux tasks, we propose, in this paper, an integrated scheduler architecture, called SchedISA, which aims to considerably reduce the execution overhead of real-time tasks in these systems. In order to test the efficacy of the proposed scheduler, we implemented partitioned earliest deadline first (P-EDF) scheduling algorithm in SchedISA on Linux kernel, version 3.8, and conducted experiments on Intel core i7 processor with eight logical cores. We compared the execution overhead of real-time tasks in the above implementation of SchedISA with that in SCHED_DEADLINE's P-EDF implementation, which concurrently executes real-time and non-real-time tasks in Linux OS in all the cores. The experimental results show that the execution overhead of real-time tasks in the above implementation of SchedISA is considerably less than that in SCHED_DEADLINE. We believe that, with further refinement of SchedISA, the execution overhead of real-time tasks in SchedISA can be reduced to a predictable maximum, making it suitable for scheduling hard real-time tasks without affecting the CPU share of Linux tasks.

Self-Assembled Discrete Molecules for Sensing Nitroaromatics

Efficient sensing of trace amount nitroaromatic (NAC) explosives has become a major research focus in recent time due to concerns over national security as well as their role as environment pollutants. NO2-containing electron-deficient aromatic compounds, such as picric acid (PA), trinitrotoluene (TNT), and dinitrotoluene (DNT), are the common constituents of many commercially available chemical explosives. In this article, we have summarized our recent developments on the rational design of electron-rich self-assembled discrete molecular sensors and their efficacy in sensing nitroaromatics both in solution as well as in vapor phase. Several p-electron-rich fluorescent metallacycles (squares, rectangles, and tweezers/pincers) and metallacages (trigonal and tetragonal prisms) have been synthesized by means of metal-ligand coordination-bonding interactions, with enough internal space to accommodate electron-deficient nitroaromatics at the molecular level by multiple supramolecular interactions. Such interactions subsequently result in the detectable fluorescence quenching of sensors even in the presence of trace quantities of nitroaromatics. The fascinating sensing characteristics of molecular architectures discussed in this article may enable future development of improved sensors for nitroaromatic explosives.

An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations

The Lattice-Boltzmann method (LBM), a promising new particle-based simulation technique for complex and multiscale fluid flows, has seen tremendous adoption in recent years in computational fluid dynamics. Even with a state-of-the-art LBM solver such as Palabos, a user has to still manually write the program using library-supplied primitives. We propose an automated code generator for a class of LBM computations with the objective to achieve high performance on modern architectures. Few studies have looked at time tiling for LBM codes. We exploit a key similarity between stencils and LBM to enable polyhedral optimizations and in turn time tiling for LBM. We also characterize the performance of LBM with the Roofline performance model. Experimental results for standard LBM simulations like Lid Driven Cavity, Flow Past Cylinder, and Poiseuille Flow show that our scheme consistently outperforms Palabos-on average by up to 3x while running on 16 cores of an Intel Xeon (Sandybridge). We also obtain an improvement of 2.47x on the SPEC LBM benchmark.

Multifarious facets of sugar-derived molecular gels: molecular features, mechanisms of self-assembly and emerging applications

The remarkable capability of nature to design and create excellent self-assembled nano-structures, especially in the biological world, has motivated chemists to mimic such systems with synthetic molecular and supramolecular systems. The hierarchically organized self-assembly of low molecular weight gelators (LMWGs) based on non-covalent interactions has been proven to be a useful tool in the development of well-defined nanostructures. Among these, the self-assembly of sugar-derived LMWGs has received immense attention because of their propensity to furnish biocompatible, hierarchical, supramolecular architectures that are macroscopically expressed in gel formation. This review sheds light on various aspects of sugar-derived LMWGs, uncovering their mechanisms of gelation, structural analysis, and tailorable properties, and their diverse applications such as stimuli-responsiveness, sensing, self-healing, environmental problems, and nano and biomaterials synthesis.

Design and morphology control of a thiophene derivative through electrospraying using various solvents

In the present work, electrospraying of an organic molecule is carried out using various solvents, obtaining fibril structures along with a range of distinct morphologies. Solvent characteristics play a major role in determining the morphology of the organic material. A thiophene derivative (7,9-di(thiophen-2-yl)-8H-cyclopentaa]acenaphthylen-8-one) (DTCPA) of donor-acceptor-donor (DAD) architecture is used to study this solvent effect. Seven solvents with decreasing vapour pressure are selected for experiments. Electrospraying is conducted at a solution concentration of 1.5 wt% and a constant applied voltage of 15 kV. Gradual transformation in morphology of the electrospun product from spiked-spheres to only spikes is observed. A mechanism describing this transformation is proposed based on electron micrograph analysis and XRD analysis. These data indicate that the morphological change is due to the synergistic effect of both vapour pressure and dielectric constant of the solvents. Through a reasonable control of the crystallite size and morphology along with the proposal of the transformation mechanism, this study elucidates electrospraying as a prospective method for designing architectures in organic electronics.

Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat

The growing number of applications and processing units in modern Multiprocessor Systems-on-Chips (MPSoCs) come along with reduced time to market. Different IP cores can come from different vendors, and their trust levels are also different, but typically they use Network-on-Chip (NoC) as their communication infrastructure. An MPSoC can have multiple Trusted Execution Environments (TEEs). Apart from performance, power, and area research in the field of MPSoC, robust and secure system design is also gaining importance in the research community. To build a secure system, the designer must know beforehand all kinds of attack possibilities for the respective system (MPSoC). In this paper we survey the possible attack scenarios on present-day MPSoCs and investigate a new attack scenario, i.e., router attack targeted toward NoC architecture. We show the validity of this attack by analyzing different present-day NoC architectures and show that they are all vulnerable to this type of attack. By launching a router attack, an attacker can control the whole chip very easily, which makes it a very serious issue. Both routing tables and routing logic-based routers are vulnerable to such attacks. In this paper, we address attacks on routing tables. We propose different monitoring-based countermeasures against routing table-based router attack in an MPSoC having multiple TEEs. Synthesis results show that proposed countermeasures, viz. Runtime-monitor, Restart-monitor, Intermediate manager, and Auditor, occupy areas that are 26.6, 22, 0.2, and 12.2 % of a routing table-based router area. Apart from these, we propose Ejection address checker and Local monitoring module inside a router that cause 3.4 and 10.6 % increase of a router area, respectively. Simulation results are also given, which shows effectiveness of proposed monitoring-based countermeasures.

Co-Exploration of NLA Kernels and Specification of Compute Elements in Distributed Memory CGRAs

Coarse Grained Reconfigurable Architectures (CGRA) are emerging as embedded application processing units in computing platforms for Exascale computing. Such CGRAs are distributed memory multi- core compute elements on a chip that communicate over a Network-on-chip (NoC). Numerical Linear Algebra (NLA) kernels are key to several high performance computing applications. In this paper we propose a systematic methodology to obtain the specification of Compute Elements (CE) for such CGRAs. We analyze block Matrix Multiplication and block LU Decomposition algorithms in the context of a CGRA, and obtain theoretical bounds on communication requirements, and memory sizes for a CE. Support for high performance custom computations common to NLA kernels are met through custom function units (CFUs) in the CEs. We present results to justify the merits of such CFUs.