Content Based Integration of Construction Site Images in Architecture, Engineering, Construction, and Facilities Management (AEC/FM) Model based Systems

This book explores the processes for retrieval, classification, and integration of construction images in AEC/FM model based systems. The author describes a combination of techniques from the areas of image and video processing, computer vision, information retrieval, statistics and content-based image and video retrieval that have been integrated into a novel method for the retrieval of related construction site image data from components of a project model. This method has been tested on available construction site images from a variety of sources like past and current building construction and transportation projects and is able to automatically classify, store, integrate and retrieve image data files in inter-organizational systems so as to allow their usage in project management related tasks. objects. Therefore, automated methods for the integration of construction images are important for construction information management. During this research, processes for retrieval, classification, and integration of construction images in AEC/FM model based systems have been explored. Specifically, a combination of techniques from the areas of image and video processing, computer vision, information retrieval, statistics and content-based image and video retrieval have been deployed in order to develop a methodology for the retrieval of related construction site image data from components of a project model. This method has been tested on available construction site images from a variety of sources like past and current building construction and transportation projects and is able to automatically classify, store, integrate and retrieve image data files in inter-organizational systems so as to allow their usage in project management related tasks.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

Architecture research and hardware implementation on simplified neural computing system for face identification

This paper describes a special-purpose neural computing system for face identification. The system architecture and hardware implementation are introduced in detail. An algorithm based on biomimetic pattern recognition has been embedded. For the total 1200 tests for face identification, the false rejection rate is 3.7% and the false acceptance rate is 0.7%.

Guest inducing p-sulfonatocalix[4] arene into three-dimensional capsule architecture and a mixed A-B double layer framework

The reactions of sodium p-sulfonatocalix[4]arene (Na5L) and terbium/europium(III) chloride in the presence of pyrazine-N,N'-dioxide (PNNO) in aqueous solutions gave the crystalline complexes 1 and 2. Both structures contain molecular capsules of p-sulfonatocalix[4] arene with PNNO as guest molecules in the cavity of the calix[4]arenes. The molecular capsules are connected through sodium and terbium (or europium) centers forming a three-dimensional framework.

Self-assembled 3D microflowery In(OH)(3) architecture and its conversion to In2O3

Using sodium dodecyl sulfate (SDS), a 3D microflowery indium hydroxide [In(OH)(3)] structure assembled from 2D nanoflakes was fabricated in a large quantity via a hydrothermal approach at relative low temperature. The obtained In(OH)(3) flowers exhibited a narrow size range between 4 and 6 mu m. The properties of these composites were characterized by XRD, EDX, FE-SEM, TEM, SAED, and TGA. In this work, both the use of urea and SDS and the amounts of these components played important roles in the formation of In(OH)3 with different nanostructures.

Self-assembly of lambda-DNA networks/Ag nanoparticles: Hybrid architecture and active-SERS substrate

In this article, highly rough and stable surface enhanced Raman scattering (SERS)-active substrates had been fabricated by a facile layer by-layer technique. Unique lambda-DNA networks and CTAB capped silver nanoparticles (AgNP) were alternatively self-assembled on the charged mica surface until a desirable number of bilayers were reached. The as-prepared hybrid architectures were characterized by UV-vis spectroscopy, tapping mode atomic force microscopy (AFM) and confocal Raman microscopy, respectively.

Macroscopic single-crystal tubes assembled with porous supramolecular architecture of water-soluble calixarene and phenanthroline

Single-crystal tubular products on the millimetre scale have been synthesized from water-soluble calixarene and phenanthroline in the presence of lanthanides by a hydrothermal method, in which the extended structures contain some 1D infinite channels.

Indian Architecture: Social and Political Challenges

The objective of this paper is to reassess the central factors which have shaped the Indian architecture. The author puts forward the concept of plurality introduced by Western art historians and argues that the diversity of the Indian architecture should not be explained in terms of religious differences, but in terms of the socio-economical situation in South Asia. He also elaborates on the Hindu caste system and its impact on the Indian architecture.

Fusion Artmap: A Neural Network Architecture for Multi-Channel Data Fusion and Classification

Fusion ARTMAP is a self-organizing neural network architecture for multi-channel, or multi-sensor, data fusion. Single-channel Fusion ARTMAP is functionally equivalent to Fuzzy ART during unsupervised learning and to Fuzzy ARTMAP during supervised learning. The network has a symmetric organization such that each channel can be dynamically configured to serve as either a data input or a teaching input to the system. An ART module forms a compressed recognition code within each channel. These codes, in turn, become inputs to a single ART system that organizes the global recognition code. When a predictive error occurs, a process called paraellel match tracking simultaneously raises vigilances in multiple ART modules until reset is triggered in one of them. Parallel match tracking hereby resets only that portion of the recognition code with the poorest match, or minimum predictive confidence. This internally controlled selective reset process is a type of credit assignment that creates a parsimoniously connected learned network. Fusion ARTMAP's multi-channel coding is illustrated by simulations of the Quadruped Mammal database.