A novel modeling approach for design studies of brushless doubly fed induction generator based on magnetic equivalent circuit

Brushless doubly fed induction generator (BDFIG) has substantial benefits, which make it an attractive alternative as a wind turbine generator. However, it suffers from lower efficiency and larger dimensions in comparison to DFIG. Hence, optimizing the BDFIG structure is necessary for enhancing its situation commercially. In previous studies, a simple model has been used in BDFIG design procedure that is insufficiently accurate. Furthermore, magnetic saturation and iron loss are not considered because of difficulties in determination of flux density distributions. The aim of this paper is to establish an accurate yet computationally fast model suitable for BDFIG design studies. The proposed approach combines three equivalent circuits including electric, magnetic and thermal models. Utilizing electric equivalent circuit makes it possible to apply static form of magnetic equivalent circuit, because the elapsed time to reach steady-state results in the dynamic form is too long for using in population-based design studies. The operating characteristics, which are necessary for evaluating the objective function and constraints values of the optimization problem, can be calculated using the presented approach considering iron loss, saturation, and geometrical details. The simulation results of a D-180 prototype BDFIG are compared with measured data in order to validate the developed model. © 1986-2012 IEEE.

Oxide electronics for imaging and displays

Despite material weaknesses, considerable progress has been made in designing large area systems such as displays and imaging arrays. This talk will address the various large area technologies, and in particular, review amorphous oxide semiconductors and associated design approaches, along with driving schemes for displays, imaging and other applications. © 2013 IEEE.

Parabolic tapered photonic crystal cavity in silicon

We demonstrate the design, fabrication, transmission spectrum measurement, and near-field characterization of a parabolic tapered one-dimensional photonic crystal cavity in silicon. The results shows a relatively high quality factor (∼43 000), together with a small modal volume of ∼ 1. 1 (λ/n) 3. Moreover, the design allows repeatable device fabrication, as evident by the similar characteristics obtained for several tens of devices that were fabricated and tested. These demonstrated 1D PhC cavities may be used as a building block in integrated photonic circuits for optical on-chip interconnects and sensing applications. © 2012 American Institute of Physics.

Understanding the cascode switching process

Cascode circuits are useful for driving normally-on wide-bandgap devices, but the switching process must be properly understood to optimise their design. Little detailed consideration has previously been given to this. This paper proposes an idealised mathematical description of the cascode switching process, which is used to show that the stray inductance between the two devices plays a critical role in switching. This idealised model is used to propose methods for optimising cascode performance in different applications. © 2013 IEEE.

Optimal recall from bounded metaplastic synapses: predicting functional adaptations in hippocampal area CA3.

A venerable history of classical work on autoassociative memory has significantly shaped our understanding of several features of the hippocampus, and most prominently of its CA3 area, in relation to memory storage and retrieval. However, existing theories of hippocampal memory processing ignore a key biological constraint affecting memory storage in neural circuits: the bounded dynamical range of synapses. Recent treatments based on the notion of metaplasticity provide a powerful model for individual bounded synapses; however, their implications for the ability of the hippocampus to retrieve memories well and the dynamics of neurons associated with that retrieval are both unknown. Here, we develop a theoretical framework for memory storage and recall with bounded synapses. We formulate the recall of a previously stored pattern from a noisy recall cue and limited-capacity (and therefore lossy) synapses as a probabilistic inference problem, and derive neural dynamics that implement approximate inference algorithms to solve this problem efficiently. In particular, for binary synapses with metaplastic states, we demonstrate for the first time that memories can be efficiently read out with biologically plausible network dynamics that are completely constrained by the synaptic plasticity rule, and the statistics of the stored patterns and of the recall cue. Our theory organises into a coherent framework a wide range of existing data about the regulation of excitability, feedback inhibition, and network oscillations in area CA3, and makes novel and directly testable predictions that can guide future experiments.

A 40 Gb/s optical bus for optical backplane interconnections

Optical technologies have received large interest in recent years for use in board-level interconnects. Polymer multimode waveguides in particular, constitute a promising technology for high-capacity optical backplanes as they can be cost-effectively integrated onto conventional printed circuit boards (PCBs). This paper presents the first optical backplane demonstrator based on the use of PCB-integrated polymer multimode waveguides and a regenerative shared bus architecture. The backplane demonstrator is formed with commercially-available low-cost electronic and photonic components onto conventional FR4 substrates and comprises two opto-electronic (OE) bus modules interconnected via a prototype regenerator unit. The system enables interconnection between the connected cards over four optical channels, each operating at 10 Gb/s. Bus extension is achieved by cascading OE bus modules via 3R regenerator units, overcoming therefore the inherent limitation of optical bus topologies in the maximum number of cards that can be connected to the bus. Details of the design, fabrication, and assembly of the different parts of this optical bus backplane are presented and related optical and data transmission characterisation studies are reported. The optical layer of the OE bus modules comprises a four-channel three-card waveguide layout that is compatible with VCSEL/PD arrays and ribbon fibres. All on-board optical paths exhibit insertion losses below 13 dB and intra-channel crosstalk lower than -29 dB. The robustness of the signal distribution from the bus inputs to all respective bus output ports in the presence of input misalignment is demonstrated, while 1 dB input alignment tolerances of approximately ±10 μm are obtained. The electrical layer of the OE bus modules comprises the essential driving circuitry for 1×4 VCSEL and PD arrays and the corresponding control and power regulation circuits. The interface between the optical and electrical layers of the bus modules is achieved with simple OE connectors that enable end-fired optical coupling into and out of the on-board polymer waveguides. The backplane demonstrator achieves error-free (BER < 10-12) 10 Gb/s data transmission over each optical channel, enabling therefore, an aggregate interconnection capacity of 40 Gb/s between any connected cards. © 1983-2012 IEEE.

Amorphous silicon thin film transistor biosensing system

Electronic systems are a very good platform for sensing biological signals for fast point-of-care diagnostics or threat detection. One of the solutions is the lab-on-a-chip integrated circuit (IC), which is low cost and high reliability, offering the possibility for label-free detection. In recent years, similar integrated biosensors based on the conventional complementary metal oxide semiconductor (CMOS) technology have been reported. However, post-fabrication processes are essential for all classes of CMOS biochips, requiring biocompatible electrode deposition and circuit encapsulation. In this work, we present an amorphous silicon (a-Si) thin film transistor (TFT) array based sensing approach, which greatly simplifies the fabrication procedures and even decreases the cost of the biosensor. The device contains several identical sensor pixels with amplifiers to boost the sensitivity. Ring oscillator and logic circuits are also integrated to achieve different measurement methodologies, including electro-analytical methods such as amperometric and cyclic voltammetric modes. The system also supports different operational modes. For example, depending on the required detection arrangement, a sample droplet could be placed on the sensing pads or the device could be immersed into the sample solution for real time in-situ measurement. The entire system is designed and fabricated using a low temperature TFT process that is compatible to plastic substrates. No additional processing is required prior to biological measurement. A Cr/Au double layer is used for the biological-electronic interface. The success of the TFT-based system used in this work will open new avenues for flexible label-free or low-cost disposable biosensors. © 2013 Materials Research Society.

Modeling current-voltage behaviour in oxide TFTs combining trap-limited conduction with percolation

Current-voltage behaviour of oxide TFTs is modeled based on trap-limited conduction and percolation theories. The mobility has a power-law dependence, in which percolation controls the exponent while trap states determine constant term in the power law. The proposed model, which is fully physically-based, provides a good agreement with measured transistor characteristics as well as transient operations of fabricated pixel test circuits for oxide-based OLED displays. © 2013 Society for Information Display.

Twitching in sensorimotor development from sleeping rats to robots.

It is still not known how the 'rudimentary' movements of fetuses and infants are transformed into the coordinated, flexible and adaptive movements of adults. In addressing this important issue, we consider a behavior that has been perennially viewed as a functionless by-product of a dreaming brain: the jerky limb movements called myoclonic twitches. Recent work has identified the neural mechanisms that produce twitching as well as those that convey sensory feedback from twitching limbs to the spinal cord and brain. In turn, these mechanistic insights have helped inspire new ideas about the functional roles that twitching might play in the self-organization of spinal and supraspinal sensorimotor circuits. Striking support for these ideas is coming from the field of developmental robotics: when twitches are mimicked in robot models of the musculoskeletal system, the basic neural circuitry undergoes self-organization. Mutually inspired biological and synthetic approaches promise not only to produce better robots, but also to solve fundamental problems concerning the developmental origins of sensorimotor maps in the spinal cord and brain.

Rashba electron transport in one-dimensional quantum waveguides

The properties of Rashba wave function in the planar one-dimensional waveguide are studied, and the following results are obtained. Due to the Rashba effect, the plane waves of electron with the energy E divide into two kinds of waves with the wave vectors k(1)=k(0)+k(delta) and k(2)=k(0)-k(delta), where k(delta) is proportional to the Rashba coefficient, and their spin orientations are +pi/2 (spin up) and -pi/2 (spin down) with respect to the circuit, respectively. If there is gate or ferromagnetic contact in the circuit, the Rashba wave function becomes standing wave form exp(+/- ik(delta)l)sin[k(0)(l-L)], where L is the position coordinate of the gate or contact. Unlike the electron without considering the spin, the phase of the Rashba plane or standing wave function depends on the direction angle theta of the circuit. The travel velocity of the Rashba waves with the wave vector k(1) or k(2) are the same hk(0)/m*. The boundary conditions of the Rashba wave functions at the intersection of circuits are given from the continuity of wave functions and the conservation of current density. Using the boundary conditions of Rashba wave functions we study the transmission and reflection probabilities of Rashba electron moving in several structures, and find the interference effects of the two Rashba waves with different wave vectors caused by ferromagnetic contact or the gate. Lastly we derive the general theory of multiple branches structure. The theory can be used to design various spin polarized devices.

Fabrication of a Low-Loss SSC Using High-Dose Electron Beam Lithography Exposure With Negative PMMA Resist

A silicon-on-insulator optical fiber-to-waveguide spot-size converter (SSC) using Poly-MethylMethAcrylate (PMMA) is presented for integrated optical circuits. Unlike the conventional use of PMMA as a positive resist, it has been successfully used as a negative resist with high-dose electron exposure for the fabrication of ultrafine silicon wire waveguides. Additionally, this process is able to reduce the side-wall roughness, and substantially depresses the unwanted propagation loss. Exploiting this technology, the authors demonstrated that the SSC can improve coupling efficiency by as much as over 2.5 dB per coupling facet, compared with that of SSC fabricated with PMMA as a positive resist with the same dimension.

Design of novel polarization beam splitter in two-dimensional photonic crystal

We present the design and the simulation of an ultracompact high efficiency polarization beam splitter (PBS) based on the properties of the light waves propagating in straight waveguide and composite structure photonic crystal. The splitting properties of the PBS are numerically simulated and analyzed by using the plane wave expansion (PWE) method and finite difference time domain (FDTD) method. The PBS consists of three parts, namely, input waveguide, beam structure and output waveguide. It is shown that a high efficiency and a large separating angle for TE mode and TM mode can be achieved. Owing to these excellent features, including small size and high rate, the PBS makes a promising candidate in the future photonic integrated circuits.

Smart universal multiple-valued logic gates by transferring single electrons

This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SEs). The logic gates are based on MOSFET based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the MOSFET based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.

Compact voltage-mode multi-valued literal gate using nanoscale ballistic MOSFETs

A CMOS voltage-mode multi-valued literal gate is presented. The ballistic electron transport characteristic of nanoscale MOSFETs is smartly used to compactly achieve universal radix-4 literal operations. The proposed literal gates have small numbers of transistors and low power dissipations, which makes them promising for future nanoscale multi-valued circuits. The gates are simulated by HSPICE.

A programmable SIMD vision chip for real-time vision applications

A programmable vision chip for real-time vision applications is presented. The chip architecture is a combination of a SIMD processing element array and row-parallel processors, which can perform pixel-parallel and row-parallel operations at high speed. It implements the mathematical morphology method to carry out low-level and mid-level image processing and sends out image features for high-level image processing without I/O bottleneck. The chip can perform many algorithms through software control. The simulated maximum frequency of the vision chip is 300 MHz with 16 x 16 pixels resolution. It achieves the rate of 1000 frames per second in real-time vision. A prototype chip with a 16 x 16 PE array is fabricated by the 0.18 mu m standard CMOS process. It has a pixel size of 30 mu m x 40 mu m and 8.72 mW power consumption with a 1.8 V power supply. Experiments including the mathematical morphology method and target tracking application demonstrated that the chip is fully functional and can be applied in real-time vision applications.