Application of a Generic Curriculum Change Management Process to Motivate and Excite Students

The School of Mechanical and Aerospace Engineering at Queen’s University Belfast is committed to enhancing the quality of student learning. A plan to implement curriculum change around this goal has been formulated and is already several years underway. A specific part of the plan involved instigating a first year introductory module to engage the students in the practice of their engineering discipline. The complicated nature of devising this type of module with regard to objectives, resources, timeframe and the number of students involved meant that a very systematic approach had to be adopted. This paper presents the simple but definitive change management process that facilitated in the creation of a first year Introduction to Engineering module. The generic nature of this process is described and its application to other facets of curriculum change is discussed. Within this process the importance of collaboration to establish a forward momentum is emphasised. This enables academic staff to progress as a group and build curriculum development based on their own experiences, expertise and established practice

Special issue on design and programming of signal processors for multimedia communication:Special issue on design and programming of signal processors for multimedia communication

The technical challenges in the design and programming of signal processors for multimedia communication are discussed. The development of terminal equipment to meet such demand presents a significant technical challenge, considering that it is highly desirable that the equipment be cost effective, power efficient, versatile, and extensible for future upgrades. The main challenges in the design and programming of signal processors for multimedia communication are, general-purpose signal processor design, application-specific signal processor design, operating systems and programming support and application programming. The size of FFT is programmable so that it can be used for various OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T) and digital video broadcasting-handheld (DVB-H). The clustered architecture design and distributed ping-pong register files in the PAC DSP raise new challenges of code generation.

Bandwidth limitation of two-port fed and self-phased quadrifilar helix antennas

The bandwidth of a resonant quadrifilar helix antenna (QHA) is shown to be strongly dependent on the design of the feed network. In this paper, we compare the impedance and radiation-pattern performance of two QHAs driven by different feed arrangements. A qualitative explanation for the difference in the behaviour of the antenna is given by observing the amplitude and phase distribution of the current in the helices. (c) 2005 Wiley Periodicals, Inc.

Neural modelling, control and optimisation of an industrial grinding process

This paper describes the development of neural model-based control strategies for the optimisation of an industrial aluminium substrate disk grinding process. The grindstone removal rate varies considerably over a stone life and is a highly nonlinear function of process variables. Using historical grindstone performance data, a NARX-based neural network model is developed. This model is then used to implement a direct inverse controller and an internal model controller based on the process settings and previous removal rates. Preliminary plant investigations show that thickness defects can be reduced by 50% or more, compared to other schemes employed. (c) 2004 Elsevier Ltd. All rights reserved.

System oriented neural networks - Problem formulation, methodology and application

A novel methodology is proposed for the development of neural network models for complex engineering systems exhibiting nonlinearity. This method performs neural network modeling by first establishing some fundamental nonlinear functions from a priori engineering knowledge, which are then constructed and coded into appropriate chromosome representations. Given a suitable fitness function, using evolutionary approaches such as genetic algorithms, a population of chromosomes evolves for a certain number of generations to finally produce a neural network model best fitting the system data. The objective is to improve the transparency of the neural networks, i.e. to produce physically meaningful

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Design and optimization of FinFETs for ultra-low-voltage analog applications

In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic de gain (A(vo)) and cutoff frequency (f(T)) for 60 and 30 nm FinFETs operated at low drive current (J(ds) = 5 mu A/mu m). The improved Avo and fT are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

Source/drain extension region engineering in FinFETs for low-voltage analog applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.

The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance

In this paper, the analogue performance of a 65 nm node double gate Sol (DGSOI) is qualitatively investigated using MixedMode simulation. The intrinsic resistance of the device is optimised by evaluating the impact of the source/drain engineering using variation of spacers and doping profile on the RF key figures of merit such as f(T), and f(MAX). It is evident that longer spacers, which approach the length of the gate offer better RF performance irrespective of the profile as long as the doping gradient at the gate edge is <7 nm/decade. Analytical expressions, which reflect the dependence of f(T), and fMAX on extrinsic source, drain and gate resistances R-S, R-D and R-G have been derived. While R-D and R-S have equal effect on f(T), R-D appears to be more influential than R-S in reducing f(MAX). The sensitivity of f(MAX) to R-S and R-D. has been shown to be greater than to R-G. (c) 2006 Elsevier Ltd. All rights reserved.

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N+ polysilicon gate device with highly doped Si layer, an asymmetrical P+/N+ polysilicon gate device with low doped Si layer and a midgap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal, gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P+/N+ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET. (C) 2004 Elsevier Ltd. All rights reserved.