System level design space exploration for MPSoC : methods, algorithms and new infrastructure

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Arquitectura VLSI orientada a la construcción de procesadores de imágenes digitales

[ES] Se presenta un modelo de arquitectura para la conexión de componentes electrónicos dentro de un chip con objeto de construir circuitos que formen parte de un procesador rápido de imágenes digitales.

Localizzazione della topoisomerasi IB sui telomeri di S. cerevisiae e ruolo della sua attività catalitica sulle modificazioni istoniche

Il superavvolgimento del DNA nelle cellule, regolato dalle DNA Topoisomerasi, influenza molti processi biologici, quali la trascrizione, la replicazione, la ricombinazione ed il rimodellamento della cromatina. La DNA Topoisomerasi IB eucariotica, (Top1), è un enzima efficiente nella rimozione dei superavvolgimenti del DNA in vitro e la sua principale funzione cellulare è la rimozione dei superavvolgimenti positivi e negativi generati durante la trascrizione e la replicazione. Risultati recenti hanno fornito evidenze sperimentali del coinvolgimento di Top1 in meccanismi multipli di regolazione dell’espressione genica eucariotica, in particolare nella fase di inizio e maturazione dei trascritti. Tuttavia, le funzioni di Top1 non sono ancora state stabilite a livello globale. Pertanto, nella presente tesi di dottorato abbiamo risposto a questa domanda con l’analisi dei profili di trascrizione genica globale e con studi di immunoprecipitazione della cromatina (ChIP) in cellule di S. cerevisiae. Circa il 9% dei geni sono influenzati da Top1, e l’analisi dei profili di espressione mostra che Top1 wt aumenta l’utilizzo del glucosio e dei pathway per la produzione di energia, con specifica diminuzione della trascrizione dei geni telomerici e subtelomerici. Abbiamo inoltre dimostrato che Top1 wt, ma non il suo mutante inattivo, aumenta la velocità di crescita cellulare nelle cellule di lievito studiate. Le analisi di ChIP mostrano che, in confronto all’assenza dell’enzima, Top1 wt diminuisce l’acetilazione dell’istone H4, compresa quella specifica della lisina 16, nel telomero destro del cromosoma XIV mentre la mutazione che inattiva l’enzima aumenta in maniera marcata l’acetilazione dell’istone H4 e la di-metilazione della lisina 4 dell’istone H3. Top1 wt incrementa anche il reclutamento di Sir3 nelle regioni di confine della cromatina silenziata dello stesso telomero. Studi di immunoprecipitazione indicano che l’enzima interagisce direttamente con la struttura della cromatina telomerica poichè entrambe le proteine, quella wt e quella inattiva, sono localizzate sulle ripetizioni telomeriche dei cromosomi di lievito. Questi risultati dimostrano che Top1, una proteina non essenziale in lievito, ottimizza i livelli globali dei trascritti per una crescita più efficiente di cellule in fase esponenziale. Indagando il meccanismo che è alla base della specifica repressione dei geni telomerici, abbiamo dimostrato che Top1 favorisce delle modifiche posttraduzionali degli istoni che indicano una struttura della cromatina repressa nelle regioni telomeriche.

New materials for electrochemiluminescence

The study of electrochemiluminescence (ECL) involves photophysical and electrochemical aspects. Excited states are populated by an electrical stimulus. The most important applications are in the diagnostic field where a number of different biologically-relevant molecules (e.g. proteins and nucleic acids) can be recognized and quantified with a sensitivity and specificity previously not reachable. As a matter of fact the electrochemistry, differently to the classic techniques as fluorescence and chemiluminescence, allows to control the excited state generation spatially and temporally. The two research visits into A. J. Bard electrochemistry laboratories were priceless. Dr. Bard has been one of ECL pioneers, the first to introduce the technique and the one who discovered in 1972 the surprising emission of Ru(bpy)3 2+. I consider necessary to thank by now my supervisors Massimo and Francesco for their help and for giving me the great opportunity to know this unique science man that made me feel enthusiastic. I will never be grateful enough… Considering that the experimental techniques of ECL did not changed significantly in these last years the most convenient research direction has been the developing of materials with new or improved properties. In Chapter I the basics concepts and mechanisms of ECL are introduced so that the successive experiments can be easily understood. In the final paragraph the scopes of the thesis are briefly described. In Chapter II by starting from ECL experimental apparatus of Dr. Bard’s laboratories the design, assembly and preliminary tests of the new Bologna instrument are carefully described. The instrument assembly required to work hard but resulted in the introduction of the new technique in our labs by allowing the continuation of the ECL studies began in Texas. In Chapter III are described the results of electrochemical and ECL studies performed on new synthesized Ru(II) complexes containing tetrazolate based ligands. ECL emission has been investigated in solution and in solid thin films. The effect of the chemical protonation of the tetrazolate ring on ECL emission has been also investigated evidencing the possibility of a catalytic effect (generation of molecular hydrogen) of one of the complexes in organic media. Finally, after a series of preliminary studies on ECL emission in acqueous buffers, the direct interaction with calf thymus DNA of some complexes has been tested by ECL and photoluminescence (PL) titration. In Chapter IV different Ir(III) complexes have been characterized electrochemically and photophysically (ECL and PL). Some complexes were already well-known in literature for their high quantum efficiency whereas the remaining were new synthesized compounds containing tetrazolate based ligands analogous to those investigated in Chapt. III. During the tests on a halogenated complex was unexpectedly evidenced the possibility to follow the kinetics of an electro-induced chemical reaction by using ECL signal. In the last chapter (V) the possibility to use mono-use silicon chips electrodes as ECL analitycal devices is under investigation. The chapter begins by describing the chip structure and materials then a signal reproducibility study and geometry optimization is carried on by using two different complexes. In the following paragraphs is reported in detail the synthesis of an ECL label based on Ru(bpy)3 2+ and the chip functionalization by using a lipoic acid SAM and the same label. After some preliminary characterizations (mass spectroscopy TOF) has been demonstrated that by mean of a simple and fast ECL measurement it’s possible to confirm the presence of the coupling product SAM-label into the chip with a very high sensitivity. No signal was detected from the same system by using photoluminescence.

Reduced-order modelling, circuit-level design and SOI fabrication of microelectromechanical resonators

This thesis deals with two important research aspects concerning radio frequency (RF) microresonators and switches. First, a new approach for compact modeling and simulation of these devices is presented. Then, a combined process flow for their simultaneous fabrication on a SOI substrate is proposed. Compact models for microresonators and switches are extracted by applying mathematical model order reduction (MOR) to the devices finite element (FE) description in ANSYS c° . The behaviour of these devices includes forms of nonlinearities. However, an approximation in the creation of the FE model is introduced, which enables the use of linear model order reduction. Microresonators are modeled with the introduction of transducer elements, which allow for direct coupling of the electrical and mechanical domain. The coupled system element matrices are linearized around an operating point and reduced. The resulting macromodel is valid for small signal analysis around the bias point, such as harmonic pre-stressed analysis. This is extremely useful for characterizing the frequency response of resonators. Compact modelling of switches preserves the nonlinearity of the device behaviour. Nonlinear reduced order models are obtained by reducing the number of nonlinearities in the system and handling them as input to the system. In this way, the system can be reduced using linear MOR techniques and nonlinearities are introduced directly in the reduced order model. The reduction of the number of system nonlinearities implies the approximation of all distributed forces in the model with lumped forces. Both for microresonators and switches, a procedure for matrices extraction has been developed so that reduced order models include the effects of electrical and mechanical pre-stress. The extraction process is fast and can be done automatically from ANSYS binary files. The method has been applied for the simulation of several devices both at devices and circuit level. Simulation results have been compared with full model simulations, and, when available, experimental data. Reduced order models have proven to conserve the accuracy of finite element method and to give a good description of the overall device behaviour, despite the introduced approximations. In addition, simulation is very fast, both at device and circuit level. A combined process-flow for the integrated fabrication of microresonators and switches has been defined. For this purpose, two processes that are optimized for the independent fabrication of these devices are merged. The major advantage of this process is the possibility to create on-chip circuit blocks that include both microresonators and switches. An application is, for example, aswitched filter bank for wireless transceiver. The process for microresonators fabrication is characterized by the use of silicon on insulator (SOI) wafers and on a deep reactive ion etching (DRIE) step for the creation of the vibrating structures in single-crystal silicon and the use of a sacrificial oxide layer for the definition of resonator to electrode distance. The fabrication of switches is characterized by the use of two different conductive layers for the definition of the actuation electrodes and by the use of a photoresist as a sacrificial layer for the creation of the suspended structure. Both processes have a gold electroplating step, for the creation of the resonators electrodes, transmission lines and suspended structures. The combined process flow is designed such that it conserves the basic properties of the original processes. Neither the performance of the resonators nor the performance of the switches results affected by the simultaneous fabrication. Moreover, common fabrication steps are shared, which allows for cheaper and faster fabrication.

Applicazioni di tecniche di manutenzione programmata presso un'industria di lavorazione carni

Integrazione nella realtà aziedale di un sistema informatizzato di gestione della manutenzione - CMMS -

Interconnection systems for highly integrated computation devices

The sustained demand for faster,more powerful chips has beenmet by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SOC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MPSOC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NOCS) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the on-chip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation focuses on all of the above points, by describing a NoC architectural implementation called ×pipes; a NoC simulation environment within a cycle-accurate MPSoC emulator called MPARM; a NoC design flow consisting of a front-end tool for optimal NoC instantiation, called SunFloor, and a set of back-end facilities for the study of NoC physical implementations. This dissertation proves the viability of NoCs for current and upcoming designs, by outlining their advantages (alongwith a fewtradeoffs) and by providing a full NoC implementation framework. It also presents some examples of additional extensions of NoCs, allowing e.g. for increased fault tolerance, and outlines where NoCsmay find further application scenarios, such as in stacked chips.

Memory hierarchy and data communication in heterogeneous reconfigurable SoCs

The miniaturization race in the hardware industry aiming at continuous increasing of transistor density on a die does not bring respective application performance improvements any more. One of the most promising alternatives is to exploit a heterogeneous nature of common applications in hardware. Supported by reconfigurable computation, which has already proved its efficiency in accelerating data intensive applications, this concept promises a breakthrough in contemporary technology development. Memory organization in such heterogeneous reconfigurable architectures becomes very critical. Two primary aspects introduce a sophisticated trade-off. On the one hand, a memory subsystem should provide well organized distributed data structure and guarantee the required data bandwidth. On the other hand, it should hide the heterogeneous hardware structure from the end-user, in order to support feasible high-level programmability of the system. This thesis work explores the heterogeneous reconfigurable hardware architectures and presents possible solutions to cope the problem of memory organization and data structure. By the example of the MORPHEUS heterogeneous platform, the discussion follows the complete design cycle, starting from decision making and justification, until hardware realization. Particular emphasis is made on the methods to support high system performance, meet application requirements, and provide a user-friendly programmer interface. As a result, the research introduces a complete heterogeneous platform enhanced with a hierarchical memory organization, which copes with its task by means of separating computation from communication, providing reconfigurable engines with computation and configuration data, and unification of heterogeneous computational devices using local storage buffers. It is distinguished from the related solutions by distributed data-flow organization, specifically engineered mechanisms to operate with data on local domains, particular communication infrastructure based on Network-on-Chip, and thorough methods to prevent computation and communication stalls. In addition, a novel advanced technique to accelerate memory access was developed and implemented.

Luminescent Systems for Genomics and Proteomics

The present PhD project was focused on the development of new tools and methods for luminescence-based techniques. In particular, the ultimate goal was to present substantial improvements to the currently available technologies for both research and diagnostic in the fields of biology, proteomics and genomics. Different aspects and problems were investigated, requiring different strategies and approaches. The whole work was thus divided into separate chapters, each based on the study of one specific aspect of luminescence: Chemiluminescence, Fluorescence and Electrochemiluminescence. CHAPTER 1, Chemiluminescence The work on luminol-enhancer solution lead to a new luminol solution formulation with 1 order of magnitude lower detection limit for HRP. This technology was patented with Cyanagen brand and is now sold worldwide for Western Blot and ELISA applications. CHAPTER 2, Fluorescescence The work on dyed-doped silica nanoparticles is marking a new milestone in the development of nanotechnologies for biological applications. While the project is still in progress, preliminary studies on model structures are leading to very promising results. The improved brightness of these nano-sized objects, their simple synthesis and handling, their low toxicity will soon turn them, we strongly believe, into a new generation of fluorescent labels for many applications. CHAPTER 3, Electrochemiluminescence The work on electrochemiluminescence produced interesting results that can potentially turn into great improvements from an analytical point of view. Ru(bpy)3 derivatives were employed both for on-chip microarray (Chapter 3.1) and for microscopic imaging applications (Chapter 3.2). The development of these new techniques is still under investigation, but the obtained results confirm the possibility to achieve the final goal. Furthermore the development of new ECL-active species (Chapter 3.3, 3.4, 3.5) and their use in these applications can significantly improve overall performances, thus helping to spread ECL as powerful analytical tool for routinary techniques. To conclude, the results obtained are of strong value to largely increase the sensitivity of luminescence techniques, thus fulfilling the expectation we had at the beginning of this research work.

Tecniche di progettazione tollerante alle variazioni per circuiti digitali in tecnologie nanometriche

The digital electronic market development is founded on the continuous reduction of the transistors size, to reduce area, power, cost and increase the computational performance of integrated circuits. This trend, known as technology scaling, is approaching the nanometer size. The lithographic process in the manufacturing stage is increasing its uncertainty with the scaling down of the transistors size, resulting in a larger parameter variation in future technology generations. Furthermore, the exponential relationship between the leakage current and the threshold voltage, is limiting the threshold and supply voltages scaling, increasing the power density and creating local thermal issues, such as hot spots, thermal runaway and thermal cycles. In addiction, the introduction of new materials and the smaller devices dimension are reducing transistors robustness, that combined with high temperature and frequently thermal cycles, are speeding up wear out processes. Those effects are no longer addressable only at the process level. Consequently the deep sub-micron devices will require solutions which will imply several design levels, as system and logic, and new approaches called Design For Manufacturability (DFM) and Design For Reliability. The purpose of the above approaches is to bring in the early design stages the awareness of the device reliability and manufacturability, in order to introduce logic and system able to cope with the yield and reliability loss. The ITRS roadmap suggests the following research steps to integrate the design for manufacturability and reliability in the standard CAD automated design flow: i) The implementation of new analysis algorithms able to predict the system thermal behavior with the impact to the power and speed performances. ii) High level wear out models able to predict the mean time to failure of the system (MTTF). iii) Statistical performance analysis able to predict the impact of the process variation, both random and systematic. The new analysis tools have to be developed beside new logic and system strategies to cope with the future challenges, as for instance: i) Thermal management strategy that increase the reliability and life time of the devices acting to some tunable parameter,such as supply voltage or body bias. ii) Error detection logic able to interact with compensation techniques as Adaptive Supply Voltage ASV, Adaptive Body Bias ABB and error recovering, in order to increase yield and reliability. iii) architectures that are fundamentally resistant to variability, including locally asynchronous designs, redundancy, and error correcting signal encodings (ECC). The literature already features works addressing the prediction of the MTTF, papers focusing on thermal management in the general purpose chip, and publications on statistical performance analysis. In my Phd research activity, I investigated the need for thermal management in future embedded low-power Network On Chip (NoC) devices.I developed a thermal analysis library, that has been integrated in a NoC cycle accurate simulator and in a FPGA based NoC simulator. The results have shown that an accurate layout distribution can avoid the onset of hot-spot in a NoC chip. Furthermore the application of thermal management can reduce temperature and number of thermal cycles, increasing the systemreliability. Therefore the thesis advocates the need to integrate a thermal analysis in the first design stages for embedded NoC design. Later on, I focused my research in the development of statistical process variation analysis tool that is able to address both random and systematic variations. The tool was used to analyze the impact of self-timed asynchronous logic stages in an embedded microprocessor. As results we confirmed the capability of self-timed logic to increase the manufacturability and reliability. Furthermore we used the tool to investigate the suitability of low-swing techniques in the NoC system communication under process variations. In this case We discovered the superior robustness to systematic process variation of low-swing links, which shows a good response to compensation technique as ASV and ABB. Hence low-swing is a good alternative to the standard CMOS communication for power, speed, reliability and manufacturability. In summary my work proves the advantage of integrating a statistical process variation analysis tool in the first stages of the design flow.

Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects

The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them. In order to overcome the limitations related to conventional structures, the researchers community is preparing different solutions, that need to be assessed. Possible solutions currently under scrutiny are represented by: • devices incorporating materials with properties different from those of silicon, for the channel and the source/drain regions; • new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits to keep under control Short–Channel–Effects without adopting high doping level in the channel. Among the solutions proposed in order to overcome the difficulties related to scaling, we can highlight heterojunctions at the channel edge, obtained by adopting for the source/drain regions materials with band–gap different from that of the channel material. This solution allows to increase the injection velocity of the particles travelling from the source into the channel, and therefore increase the performance of the transistor in terms of provided drain current. The first part of this thesis work addresses the use of heterojunctions in SOI transistors: chapter 3 outlines the basics of the heterojunctions theory and the adoption of such approach in older technologies as the heterojunction–bipolar–transistors; moreover the modifications introduced in the Monte Carlo code in order to simulate conduction band discontinuities are described, and the simulations performed on unidimensional simplified structures in order to validate them as well. Chapter 4 presents the results obtained from the Monte Carlo simulations performed on double–gate SOI transistors featuring conduction band offsets between the source and drain regions and the channel. In particular, attention has been focused on the drain current and to internal quantities as inversion charge, potential energy and carrier velocities. Both graded and abrupt discontinuities have been considered. The scaling of devices dimensions and the adoption of innovative architectures have consequences on the power dissipation as well. In SOI technologies the channel is thermally insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2 layer features a thermal conductivity that is two orders of magnitude lower than the silicon one, and it impedes the dissipation of the heat generated in the active region. Moreover, the thermal conductivity of thin semiconductor films is much lower than that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects cause severe self–heating effects, that detrimentally impact the carrier mobility and therefore the saturation drive current for high–performance transistors; as a consequence, thermal device design is becoming a fundamental part of integrated circuit engineering. The second part of this thesis discusses the problem of self–heating in SOI transistors. Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and it provides a brief overview on the methods that have been proposed in order to model these phenomena. In order to understand how this problem impacts the performance of different SOI architectures, three–dimensional electro–thermal simulations have been applied to the analysis of SHE in planar single and double–gate SOI transistors as well as FinFET, featuring the same isothermal electrical characteristics. In chapter 6 the same simulation approach is extensively employed to study the impact of SHE on the performance of a FinFET representative of the high–performance transistor of the 45 nm technology node. Its effects on the ON–current, the maximum temperatures reached inside the device and the thermal resistance associated to the device itself, as well as the dependence of SHE on the main geometrical parameters have been analyzed. Furthermore, the consequences on self–heating of technological solutions such as raised S/D extensions regions or reduction of fin height are explored as well. Finally, conclusions are drawn in chapter 7.

Enabling Blocks for Integrated CMOS UWB Transceivers

The last decades have seen an unrivaled growth and diffusion of mobile telecommunications. Several standards have been developed to this purposes, from GSM mobile phone communications to WLAN IEEE 802.11, providing different services for the the transmission of signals ranging from voice to high data rate digital communications and Digital Video Broadcasting (DVB). In this wide research and market field, this thesis focuses on Ultra Wideband (UWB) communications, an emerging technology for providing very high data rate transmissions over very short distances. In particular the presented research deals with the circuit design of enabling blocks for MB-OFDM UWB CMOS single-chip transceivers, namely the frequency synthesizer and the transmission mixer and power amplifier. First we discuss three different models for the simulation of chargepump phase-locked loops, namely the continuous time s-domain and discrete time z-domain approximations and the exact semi-analytical time-domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling time as a function of loop parameters, deriving practical conditions under which the different models are reliable for fast settling PLLs up to fourth order. Besides, a phase noise analysis method based upon the time-domain model is introduced and compared to the results obtained by means of the s-domain model. We compare the three models over the simulation of a fast switching PLL to be integrated in a frequency synthesizer for WiMedia MB-OFDM UWB systems. In the second part, the theoretical analysis is applied to the design of a 60mW 3.4 to 9.2GHz 12 Bands frequency synthesizer for MB-OFDM UWB based on two wide-band PLLs. The design is presented and discussed up to layout level. A test chip has been implemented in TSMC CMOS 90nm technology, measured data is provided. The functionality of the circuit is proved and specifications are met with state-of-the-art area occupation and power consumption. The last part of the thesis deals with the design of a transmission mixer and a power amplifier for MB-OFDM UWB band group 1. The design has been carried on up to layout level in ST Microlectronics 65nm CMOS technology. Main characteristics of the systems are the wideband behavior (1.6 GHz of bandwidth) and the constant behavior over process parameters, temperature and supply voltage thanks to the design of dedicated adaptive biasing circuits.

Applications of High Speed Configurable Logic Devices in Modern Particle Physics Experiments

Several activities were conducted during my PhD activity. For the NEMO experiment a collaboration between the INFN/University groups of Catania and Bologna led to the development and production of a mixed signal acquisition board for the Nemo Km3 telescope. The research concerned the feasibility study for a different acquisition technique quite far from that adopted in the NEMO Phase 1 telescope. The DAQ board that we realized exploits the LIRA06 front-end chip for the analog acquisition of anodic an dynodic sources of a PMT (Photo-Multiplier Tube). The low-power analog acquisition allows to sample contemporaneously multiple channels of the PMT at different gain factors in order to increase the signal response linearity over a wider dynamic range. Also the auto triggering and self-event-classification features help to improve the acquisition performance and the knowledge on the neutrino event. A fully functional interface towards the first level data concentrator, the Floor Control Module, has been integrated as well on the board, and a specific firmware has been realized to comply with the present communication protocols. This stage of the project foresees the use of an FPGA, a high speed configurable device, to provide the board with a flexible digital logic control core. After the validation of the whole front-end architecture this feature would be probably integrated in a common mixed-signal ASIC (Application Specific Integrated Circuit). The volatile nature of the configuration memory of the FPGA implied the integration of a flash ISP (In System Programming) memory and a smart architecture for a safe remote reconfiguration of it. All the integrated features of the board have been tested. At the Catania laboratory the behavior of the LIRA chip has been investigated in the digital environment of the DAQ board and we succeeded in driving the acquisition with the FPGA. The PMT pulses generated with an arbitrary waveform generator were correctly triggered and acquired by the analog chip, and successively they were digitized by the on board ADC under the supervision of the FPGA. For the communication towards the data concentrator a test bench has been realized in Bologna where, thanks to a lending of the Roma University and INFN, a full readout chain equivalent to that present in the NEMO phase-1 was installed. These tests showed a good behavior of the digital electronic that was able to receive and to execute command imparted by the PC console and to answer back with a reply. The remotely configurable logic behaved well too and demonstrated, at least in principle, the validity of this technique. A new prototype board is now under development at the Catania laboratory as an evolution of the one described above. This board is going to be deployed within the NEMO Phase-2 tower in one of its floors dedicated to new front-end proposals. This board will integrate a new analog acquisition chip called SAS (Smart Auto-triggering Sampler) introducing thus a new analog front-end but inheriting most of the digital logic present in the current DAQ board discussed in this thesis. For what concern the activity on high-resolution vertex detectors, I worked within the SLIM5 collaboration for the characterization of a MAPS (Monolithic Active Pixel Sensor) device called APSEL-4D. The mentioned chip is a matrix of 4096 active pixel sensors with deep N-well implantations meant for charge collection and to shield the analog electronics from digital noise. The chip integrates the full-custom sensors matrix and the sparsifification/readout logic realized with standard-cells in STM CMOS technology 130 nm. For the chip characterization a test-beam has been set up on the 12 GeV PS (Proton Synchrotron) line facility at CERN of Geneva (CH). The collaboration prepared a silicon strip telescope and a DAQ system (hardware and software) for data acquisition and control of the telescope that allowed to store about 90 million events in 7 equivalent days of live-time of the beam. My activities concerned basically the realization of a firmware interface towards and from the MAPS chip in order to integrate it on the general DAQ system. Thereafter I worked on the DAQ software to implement on it a proper Slow Control interface of the APSEL4D. Several APSEL4D chips with different thinning have been tested during the test beam. Those with 100 and 300 um presented an overall efficiency of about 90% imparting a threshold of 450 electrons. The test-beam allowed to estimate also the resolution of the pixel sensor providing good results consistent with the pitch/sqrt(12) formula. The MAPS intrinsic resolution has been extracted from the width of the residual plot taking into account the multiple scattering effect.

Complexity of N-Myc transcriptional function in childhood neuroblastoma

Myc is a transcription factor that can activate transcription of several hundreds genes by direct binding to their promoters at specific DNA sequences (E-box). However, recent studies have also shown that it can exert its biological role by repressing transcription. Such studies collectively support a model in which c-Myc-mediated repression occurs through interactions with transcription factors bound to promoter DNA regions but not through direct recognition of typical E-box sequences. Here, we investigated whether N-Myc can also repress gene transcription, and how this is mechanistically achieved. We used human neuroblastoma cells as a model system in that N-MYC amplification/over-expression represents a key prognostic marker of this tumour. By means of transcription profile analyses we could identify at least 5 genes (TRKA, p75NTR, ABCC3, TG2, p21) that are specifically repressed by N-Myc. Through a dual-step-ChIP assay and genetic dissection of gene promoters, we found that N-Myc is physically associated with gene promoters in vivo, in proximity of the transcription start site. N-Myc association with promoters requires interaction with other proteins, such as Sp1 and Miz1 transcription factors. Furthermore, we found that N-Myc may repress gene expression by interfering directly with Sp1 and/or with Miz1 activity (i.e. TRKA, p75NTR, ABCC3, p21) or by recruiting Histone Deacetylase 1 (Hdac1) (i.e. TG2). In vitro analyses show that distinct N-Myc domains can interact with Sp1, Miz1 and Hdac1, supporting the idea that Myc may participate in distinct repression complexes by interacting specifically with diverse proteins. Finally, results show that N-Myc, through repressed genes, affects important cellular functions, such as apoptosis, growth, differentiation and motility. Overall, our results support a model in which N-Myc, like c-Myc, can repress gene transcription by direct interaction with Sp1 and/or Miz1, and provide further lines of evidence on the importance of transcriptional repression by Myc factors in tumour biology.

Molecular characterization of the human gut microbiota: the effect of aging

Age-related physiological changes in the gastrointestinal tract, as well as modification in lifestyle, nutritional behaviour, and functionality of the host immune system, inevitably affect the gut microbiota. The study presented here is focused on the application and comparison of two different microarray approaches for the characterization of the human gut microbiota, the HITChip and the HTF-Microb.Array, with particular attention to the effects of the aging process on the composition of this ecosystem. By using the Human Intestinal Tract Chip (HITChip), recently developed at the Wageningen University, The Netherland, we explored the age-related changes of gut microbiota during the whole adult lifespan, from young adults, through elderly to centenarians. We observed that the microbial composition and diversity of the gut ecosystem of young adults and seventy-years old people is highly similar but differs significantly from that of the centenarians. After 100 years of symbiotic association with the human host, the microbiota is characterized by a rearrangement in the Firmicutes population and an enrichment of facultative anaerobes. The presence of such a compromised microbiota in the centenarians is associated with an increased inflammation status, also known as inflamm-aging, as determined by a range of peripheral blood inflammatory markers. In parallel, we overtook the development of our own phylogenetic microarray with a lower number of targets, aiming the description of the human gut microbiota structure at high taxonomic level. The resulting chip was called High Taxonomic level Fingerprinting Microbiota Array (HTF-Microb.Array), and was based on the Ligase Detection Reaction (LDR) technology, which allowed us to develop a fast and sensitive tool for the fingerprint of the human gut microbiota in terms of presence/absence of the principal groups. The validation on artificial DNA mixes, as well as the pilot study involving eight healthy young adults, demonstrated that the HTF-Microb.Array can be used to successfully characterize the human gut microbiota, allowing us to obtain results which are in approximate accordance with the most recent characterizations. Conversely, the evaluation of the relative abundance of the target groups on the bases of the relative fluorescence intensity probes response still has some hindrances, as demonstrated by comparing the HTF.Microb.Array and HITChip high taxonomic level fingerprints of the same centenarians.