978 resultados para Micro-simulation


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This paper reports the simulation results from the dynamic analysis of a Shape Memory Alloy (SMA) actuator. The emphasis is on understanding the dynamic behavior under various loading rates and boundary conditions, resulting in complex scenarios such as thermal and stress gradients. Also, due to the polycrystalline nature of SMA wires, presence of microstructural inhomogeneity is inevitable. Probing the effect of inhomogeneity on the dynamic behavior can facilitate the prediction of life and characteristics of SMA wire actuator under varieties of boundary and loading conditions. To study the effect of these factors, an initial boundary value problem of SMA wire is formulated. This is subsequently solved using finite element method. The dynamic response of the SMA wire actuator is analyzed under mechanical loading and results are reported. Effect of loading rate, micro-structural inhomogeneity and thermal boundary conditions on the dynamic response of SMA wire actuator is investigated and the simulation results are reported.

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In this paper we present and compare the results obtained from semi-classical and quantum mechanical simulation for a double gate MOSFET structure to analyze the electrostatics and carrier dynamics of this device. The geometries like gate length, body thickness of this device have been chosen according to the ITRS specification for the different technology nodes. We have shown the extent of deviation between the semi- classical and quantum mechanical results and hence the need of quantum simulations for the promising nanoscale devices in the future technology nodes predicted in ITRS.

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The conventional metal oxide semiconductor field effect transistor (MOSFET)may not be suitable for future low standby power (LSTP) applications due to its high off-state current as the sub-threshold swing is theoretically limited to 60mV/decade. Tunnel field effect transistor (TFET) based on gate controlled band to band tunneling has attracted attention for such applications due to its extremely small sub-threshold swing (much less than 60mV/decade). This paper takes a simulation approach to gain some insight into its electrostatics and the carrier transport mechanism. Using 2D device simulations, a thorough study and analysis of the electrical parameters of the planar double gate TFET is performed. Due to excellent sub-threshold characteristics and a reverse biased structure, it offers orders of magnitude less leakage current compared to the conventional MOSFET. In this work, it is shown that the device can be scaled down to channel lengths as small as 30 nm without affecting its performance. Also, it is observed that the bulk region of the device plays a major role in determining the sub-threshold characteristics of the device and considerable improvement in performance (in terms of ION/IOFF ratio) can be achieved if the thickness of the device is reduced. An ION/IOFF ratio of 2x1012 and a minimum point sub-threshold swing of 22mV/decade is obtained.