Sparse matrix multiplication on a reconfigurable many-core architecture

Sparse matrix-vector multiplication (SMVM) is a fundamental operation in many scientific and engineering applications. In many cases sparse matrices have thousands of rows and columns where most of the entries are zero, while non-zero data is spread over the matrix. This sparsity of data locality reduces the effectiveness of data cache in general-purpose processors quite reducing their performance efficiency when compared to what is achieved with dense matrix multiplication. In this paper, we propose a parallel processing solution for SMVM in a many-core architecture. The architecture is tested with known benchmarks using a ZYNQ-7020 FPGA. The architecture is scalable in the number of core elements and limited only by the available memory bandwidth. It achieves performance efficiencies up to almost 70% and better performances than previous FPGA designs.

The role of public policy in health care promotion: a comparative perspective

Comunicação apresentada na 17th International conference on Health Promotio Hospitals and Health Services em Hersonissis, Crete, Grécia de 6-8 de maio de 2009

Proposal for shared services performance management model applied to portugueses public administration

Comunicação apresentada no 8º Congresso Nacional de Administração Pública - Desafios e Soluções, em Carcavelos de 21 a 22 de Novembro de 2011.

Core language for web applications

Trabalho apresentado no âmbito do Mestrado em Engenharia Informática, como requisito parcial para obtenção do grau de Mestre em Engenharia Informática

Microencapsulation technology: a powerful tool for human embryonic stem cells expansion and cryopreservation

Dissertation presented to obtain a Master degree in Biotechnology at the Universidade Nova de Lisboa, Faculdade de Ciências e Tecnologia

Designing a technology assessment post-graduation programme: experiences, limits and needs

The post-graduation in the field of Technology Assessment (TA) is recent and that are several and different ways to be organised. Most experiences are related with the Masters diplom level (2nd cycle of graduation in high education). Just one in PhD level is explicit in the field of TA, and some other PhD courses include also TA topics in their programme structure. In this chapter we will analyse the problems related with the design of a post-graduation (MA, MSc or PhD) programme in the field of TA using as reference some international experiences. Hereby, the main conclusion seems to address labour market needs in the specialised knowledge of TA, of technology management or technology innovation. In this sense TA should be included as “minor” into post-graduation courses which may range from engineering disciplines to social sciences. As a graduation programme it can fill an expertise gap between technicians, engineers, scientists and the strategic decision makers or policy makers.

Designing a technology assessment post-graduation programme: experiences, limits and needs

IET Working Papers Series No. WPS09/2010

Technology market transfer plan launch of DELIVES to E.U. Market©

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Biotecnologia

How composite indicators of innovation can influence technology policy decision?

Based on the report for Project III of the PhD programme on Technology Assessment and prepared for the Winter School that took place at Universidade Nova de Lisboa, Caparica Campus on the 6th and 7th of December 2010.

Significance of isolated hepatitis B core antibody in blood donors from São Paulo

The clinical significance of isolated anti-HBc is still a challenge. To elucidate the real importance of this finding in our blood donors, an investigation algorithm was tested. One hundred and twelve isolated anti-HBc seropositive blood donors underwent clinical evaluation and retesting of HBV markers. Those who presented repeatedly reactive isolated anti-HBc, received a single dose of hepatitis B recombinant vaccine to verify anti-HBs early response. A HBV-DNA determination by PCR was done for those who did not test positive to anti-HBs after vaccine. The level of anti-HBc was recorded as a ratio of the sample-to-cut-off values (S:C ratio) in 57 candidates at donation. Comparing true and false-positive anti-HBc results, the different S:C ratios of them were statistically significant and when less than 2, implying in a false-positive result probability over 80%. A high percent of false-positive results (16.07%) was verified after anti-HBc retesting. HBV immunity was characterized in 49.11%, either by anti-HBs detection in retesting (15.18%), or after a single dose HBV vaccination (33.93%). HBV-DNA was negative in all tested donors. In conclusion, this algorithm was useful to clarify the meaning of isolated anti-HBc in most of our blood donors.

Synthesis about a collaborative project on “Technology Assessment of Autonomous System

The project started in 2009 with the support of DAAD in Germany and CRUP in Portugal under the “Collaborative German-Portuguese University Actions” programme. One central goal is the further development of a theory of technology assessment applied to robotics and autonomous systems in general that reflects in its methodology the changing conditions of knowledge production in modern societies and the emergence of new robotic technologies and of associated disruptive changes. Relevant topics here are handling broadened future horizons and new clusters of science and technology (medicine, engineering, interfaces, industrial automation, micro-devices, security and safety), as well as new governance structures in policy decision making concerning research and development (R

Development of molecularly imprinted polymers using supercritical fluid technology

Dissertação para obtenção do Grau de Doutor em Química Sustentável

Estimation Models for the adoption and use of information technology: internet-related technologies at firm level in the Portuguese and European context

Dissertação apresentada como requisito parcial para obtenção do grau de Doutor em Gestão de Informação

Real-Time Application Mapping for Many-Cores Using a Limited Migrative Model

Many-core platforms are an emerging technology in the real-time embedded domain. These devices offer various options for power savings, cost reductions and contribute to the overall system flexibility, however, issues such as unpredictability, scalability and analysis pessimism are serious challenges to their integration into the aforementioned area. The focus of this work is on many-core platforms using a limited migrative model (LMM). LMM is an approach based on the fundamental concepts of the multi-kernel paradigm, which is a promising step towards scalable and predictable many-cores. In this work, we formulate the problem of real-time application mapping on a many-core platform using LMM, and propose a three-stage method to solve it. An extended version of the existing analysis is used to assure that derived mappings (i) guarantee the fulfilment of timing constraints posed on worst-case communication delays of individual applications, and (ii) provide an environment to perform load balancing for e.g. energy/thermal management, fault tolerance and/or performance reasons.

An Enhanced WLAN Security System With FPGA Implementation for Multimedia Applications

Maintaining a high level of data security with a low impact on system performance is more challenging in wireless multimedia applications. Protocols that are used for wireless local area network (WLAN) security are known to significantly degrade performance. In this paper, we propose an enhanced security system for a WLAN. Our new design aims to decrease the processing delay and increase both the speed and throughput of the system, thereby making it more efficient for multimedia applications. Our design is based on the idea of offloading computationally intensive encryption and authentication services to the end systems’ CPUs. The security operations are performed by the hosts’ central processor (which is usually a powerful processor) before delivering the data to a wireless card (which usually has a low-performance processor). By adopting this design, we show that both the delay and the jitter are significantly reduced. At the access point, we improve the performance of network processing hardware for real-time cryptographic processing by using a specialized processor implemented with field-programmable gate array technology. Furthermore, we use enhanced techniques to implement the Counter (CTR) Mode with Cipher Block Chaining Message Authentication Code Protocol (CCMP) and the CTR protocol. Our experiments show that it requires timing in the range of 20–40 μs to perform data encryption and authentication on different end-host CPUs (e.g., Intel Core i5, i7, and AMD 6-Core) as compared with 10–50 ms when performed using the wireless card. Furthermore, when compared with the standard WiFi protected access II (WPA2), results show that our proposed security system improved the speed to up to 3.7 times.