Optical Characterization of Indium Gallium Nitride for Application in High-Efficiency Solar Photovoltaic Cells

The semiconductor alloy indium gallium nitride (InxGa1-xN) offers substantial potential in the development of high-efficiency multi-junction photovoltaic devices due to its wide range of direct band gaps, strong absorption and other optoelectronic properties. This work uses a variety of characterization techniques to examine the properties of InxGa1-xN thin films deposited in a range of compositions by a novel plasma-enhanced evaporation deposition system. Due to the high vapour pressure and low dissociation temperature of indium, the indium incorporation and, ultimately, control of the InxGa1-xN composition was found to be influenced to a greater degree by deposition temperature than variations in the In:Ga source rates in the investigated region of deposition condition space. Under specific deposition conditions, crystalline films were grown in an advantageous nano-columnar microstructure with deposition temperature influencing column size and density. The InxGa1-xN films were determined to have very strong absorption coefficients with band gaps indirectly related to indium content. However, the films also suffer from compositional inhomogeneity and In-related defect complexes with strong phonon coupling that dominates the emission mechanism. This, in addition to the presence of metal impurities, harms the alloy’s electronic properties as no significant photoresponse was observed. This research has demonstrated the material properties that make the InxGa1-xN alloy attractive for multi-junction solar cells and the benefits/drawbacks of the plasma-enhanced evaporation deposition system. Future work is needed to overcome significant challenges relating to crystalline quality, compositional homogeneity and the optoelectronic properties of In-rich InxGa1-xN films in order to develop high-performance photovoltaic devices.

Performance assessment of nanoscale double- and triple- gate FinFETs

This is the first paper to describe performance assessment of triple and double gate FinFETs for High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) logic technologies is investigated. The impact of gate work-function, spacer width, lateral source/drain doping gradient, fin aspect ratio, fin thickness on device performance, has been analysed in detail and guidelines are presented to meet ITRS specification at 65 and 45 nm nodes. Optimal design of lateral source/drain doping profile can not only effectively control short channel effects, yielding low off-current, but also achieve low values of intrinsic gate delay.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

Real-valued fixed-complexity sphere decoder for high dimensional QAM-MIMO systems

The development of high performance, low computational complexity detection algorithms is a key challenge for real-time Multiple-Input Multiple-Output (MIMO) communication system design. The Fixed-Complexity Sphere Decoder (FSD) algorithm is one of the most promising approaches, enabling quasi-ML decoding accuracy and high performance implementation due to its deterministic, highly parallel structure. However, it suffers from exponential growth in computational complexity as the number of MIMO transmit antennas increases, critically limiting its scalability to larger MIMO system topologies. In this paper, we present a solution to this problem by applying a novel cutting protocol to the decoding tree of a real-valued FSD algorithm. The new Real-valued Fixed-Complexity Sphere Decoder (RFSD) algorithm derived achieves similar quasi-ML decoding performance as FSD, but with an average 70% reduction in computational complexity, as we demonstrate from both theoretical and implementation perspectives for Quadrature Amplitude Modulation (QAM)-MIMO systems.

HIGH SPEED CMOS/SOS IMPLEMENTATION OF A BIT LEVEL SYSTOLIC CORRELATOR.

The fabrication and performance of the first bit-level systolic correlator array is described. The application of systolic array concepts at the bit level provides a simple and extremely powerful method for implementing high-performance digital processing functions. The resulting structure is highly regular, facilitating yield enhancement through fault-tolerant redundancy techniques and therefore ideally suited to implementation as a VLSI chip. The CMOS/SOS chip operates at 35 MHz, is fully cascadable and exhibits 64-stage correlation for 1-bit reference and 4-bit data. 7 refs.

Real-time GPU color-based segmentation of football players

In this paper, we propose a multi-camera application capable of processing high resolution images and extracting features based on colors patterns over graphic processing units (GPU). The goal is to work in real time under the uncontrolled environment of a sport event like a football match. Since football players are composed for diverse and complex color patterns, a Gaussian Mixture Models (GMM) is applied as segmentation paradigm, in order to analyze sport live images and video. Optimization techniques have also been applied over the C++ implementation using profiling tools focused on high performance. Time consuming tasks were implemented over NVIDIA's CUDA platform, and later restructured and enhanced, speeding up the whole process significantly. Our resulting code is around 4-11 times faster on a low cost GPU than a highly optimized C++ version on a central processing unit (CPU) over the same data. Real time has been obtained processing until 64 frames per second. An important conclusion derived from our study is the scalability of the application to the number of cores on the GPU. © 2011 Springer-Verlag.

LC- HRMS based metabolomics in food safety and doping control – DeTECH21

Issues surrounding the misuse of prohibited and licensed substances in animals destined for food production and performance sport competition continue to be an enormous challenge to regulatory authorities charged with enforcing their control. Efficient analytical strategies are implemented to screen and confirm the presence of a wide range of exogenous substances in various biological matrices. However, such methods rely on the direct measurement of drugs and/or their metabolites in a targeted mode, allowing the detection of restricted number of compounds. As a consequence, emerging practices, in particular the use of natural hormones, designer drugs and low-dose cocktails, remain difficult to handle from a control point of view. A new SME-led FP7 funded project, DeTECH21, aims to overcome current limitations by applying an untargeted metabolomics approach based on liquid chromatography coupled to high resolution mass spectrometry and bioinformatic data analysis to identify bovine and equine animals which have been exposed to exogenous substances and assist in the identification of administered compounds. Markerbased strategies, dealing with the comprehensive analysis of metabolites present in a biological sample (urine/plasma/tissue), offer a reliable solution in the areas of food safety and animal sport doping control by effective, high-throughput and sensitive detection of exogenously administered agents. Therefore, the development of the first commercially available forensic test service based on metabolomics profiling will meet 21st century demands in animal forensics.

High Strength Thermoplastic Bonding for Multi-channel, Multi-layer Lab-on-Chip Devices for Ocean and Environmental applications

A solvent-vapour thermoplastic bonding process is reported which provides high strength bonding of PMMA over a large area for multi-channel and multi-layer microfluidic devices with shallow high resolution channel features. The bond process utilises a low temperature vacuum thermal fusion step with prior exposure of the substrate to chloroform (CHCl3) vapour to reduce bond temperature to below the PMMA glass transition temperature. Peak tensile and shear bond strengths greater than 3 MPa were achieved for a typical channel depth reduction of 25 µm. The device-equivalent bond performance was evaluated for multiple layers and high resolution channel features using double-side and single-side exposure of the bonding pieces. A single-sided exposure process was achieved which is suited to multi-layer bonding with channel alignment at the expense of greater depth loss and a reduction in peak bond strength. However, leak and burst tests demonstrate bond integrity up to at least 10 bar channel pressure over the full substrate area of 100 mm x 100 mm. The inclusion of metal tracks within the bond resulted in no loss of performance. The vertical wall integrity between channels was found to be compromised by solvent permeation for wall thicknesses of 100 µm which has implications for high resolution serpentine structures. Bond strength is reduced considerably for multi-layer patterned substrates where features on each layer are not aligned, despite the presence of an intermediate blank substrate. Overall a high performance bond process has been developed that has the potential to meet the stringent specifications for lab-on-chip deployment in harsh environmental conditions for applications such as deep ocean profiling.

Facile synthesis of nanocrystalline LiFePO4/graphene composite as cathode material for high power lithium ion batteries

We describe a simple strategy, which is based on the idea of space confinement, for the synthesis of carbon coating on LiFePO₄ nanoparticles/graphene nanosheets composites in a water-in-oil emulsion system. The prepared composite displayed high performance as a cathode material for lithium-ion battery, such as high reversible lithium storage capacity (158 mA h g^-1 after 100 cycles), high coulombic efficiency (over 97%), excellent cycling stability and high rate capability (as high as 83 mA h g ^-1 at 60 C). Very significantly, the preparation method employed can be easily adapted and be extended as a general approach to sophisticated compositions and structures for the preparation of highly dispersed nanosized structure on graphene.