Paired interference 3-dB coupler based on SOI rib waveguides with anisotropic chemical wet etching

A 3-dB paired interference (PI) optical coupler in silicon-on-insulator (SOI) based on rib waveguides with trapezoidal cross section was designed with simulation by a modified finite-difference beam propagation method (FD-BPM) and fabricated by potassium hydroxide (KOH) anisotropic chemical wet etching. Theoretically, tolerances of width, length, and port distance are more than 1, 100, and 1 mu m, respectively. Smooth interface was obtained with the propagation loss of 1.1 dB/cm at the wavelength of 1.55 mu m. The coupler has a good uniformity of 0.2 dB and low excess loss of less than 2 dB.

Multi-channel micro neural probe fabricated with SOI

Silicon-on-insulator (SOI) substrate is widely used in micro-electro-mechanical systems (MEMS). With the buried oxide layer of SOI acting as an etching stop, silicon based micro neural probe can be fabricated with improved uniformity and manufacturability. A seven-record-site neural probe was formed by inductive-coupled plasma (ICP) dry etching of an SOI substrate. The thickness of the probe is 15 mu m. The shaft of the probe has dimensions of 3 mmx100 mu mx15 mu m with typical area of the record site of 78.5 mu m(2). The impedance of the record site was measured in-vitro. The typical impedance characteristics of the record sites are around 2 M Omega at 1 kHz. The performance of the neural probe in-vivo was tested on anesthetic rat. The recorded neural spike was typically around 140 mu V. Spike from individual site could exceed 700 mu V. The average signal noise ratio was 7 or more.

An investigation of the mode characteristics of SOI submicron rib waveguides using the film mode matching method

The mode characteristics of SOI (silicon-on-insulator) submicron rib waveguides are very different from those of micrometer-sized ones. Using the full-vector film mode matching method, we propose a simple criterion to determine whether a waveguide mode is guided or not. The single-mode condition for deep-etched waveguides is obtained using this criterion. We also obtain the inherent TM mode leakage and sharp cancelation effects due to TE-TM mode coupling in shallow-etched rib waveguides from numerical simulations, which agree well with the analytical results based on total internal reflection and interference theories.

1 x 4 Ge-on-SOI PIN Photodetector Array for Parallel Optical Interconnects

High-quality Ge film was epitaxially grown on silicon on insulator using the ultrahigh vacuum chemical vapor deposition. In this paper, we demonstrated that the efficient 1 4 germanium-on-silicon p-i-n photodetector arrays with 1.0 mu m Ge film had a responsivity as high as 0.65 A/W at 1.31 mu m and 0.32 A/W at 1.55 mu m, respectively. The dark current density was about 0.75 mA/cm(2) at 0 V and 13.9 mA/cm(2) at 1.0 V reverse bias. The detectors with a diameter of 25 mu m were measured at 1550 nm incident light under 0 V bias, and the result showed that the 3-dB bandwidth is 2.48 GHz. At a reverse bias of 3 V, the bandwidth is about 13.3 GHz. The four devices showed a good consistency.

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

Low power 2 x 2 thermo-optic SOI waveguide switch fabricated by anisotropy chemical etching

A 2 x 2 thermo-optic (TO) Mach-Zehnder (MZ) switch based on silicon waveguides with large cross section was designed and fabricated on silicon-on-insulator (SOI) wafer. The multi-mode interferometers (MMI) were used as power splitter and combiner in MZ structure. In order to get smooth interface, anisotropy chemical wet-etching of silicon was used to fabricate the waveguides instead of dry-etching. Additional grooves were introduced to reduce power consumption. The device has a low switching power of 235 mW and a switching speed of 60 mus. (C) 2004 Elsevier B.V. All rights reserved.

Rearrangeable nonblocking SOI waveguide thermooptic 4x4 switch matrix with low insertion loss and fast response

A rearrangeable nonblocking 4 x 4 thermooptic silicon-on-insulator waveguide switch matrix at 1.55-mu m integrated spot size converters is designed and fabricated for the first time. The insertion losses and polarization-dependent losses of the four channels are less than 10 and 0.8 dB, respectively. The extinction ratios are larger than 20 dB. The response times are 4.6 mu s for rising edge and 1.9 mu s for failing edge.

Integrated folding 4x4 optical matrix switch with total internal reflection mirrors on SOI by anisotropic chemical etching

A folding rearrangeable nonblocking 4 x 4 optical matrix switch was designed and fabricated on silicon-on-insulator wafer. To compress chip size, switch elements (SEs) were interconnected by total internal reflection (TIR) mirrors instead of conventional S-bends. For obtaining smooth interfaces, potassium hydroxide anisotropic chemical etching of silicon was utilized to make the matrix switch for the first time. The device has a compact size of 20 x 1.6 mm(2) and a fast response of 7.5 mu s. The power consumption of each 2 x 2 SE and the average excess loss per mirror were 145 mW and -1.1 dB, respectively. Low path dependence of +/- 0.7 dB in total excess loss was obtained because of the symmetry of propagation paths in this novel matrix switch.

Fabrication of a 4x4 strictly nonblocking SOI switch matrix

A 4 x 4 strictly nonblocking thermo-optical switch matrix based on Mach-Zehnder (MZ) switching unit was designed and fabricated in silicon-on-insulator (SOI) wafer. The paired multi-mode interferometers (MMI) were used as power splitters and combiners in MZ structures. The device presents an average insertion loss of 17 dB and an average crosstalk of 16.5 dB. The power consumption needed for operation is reduced to 0.288 W by adding isolating trenches. The switching time of the device is about 15 mu s, which is much faster than that of silica-based switches. (C) 2005 Elsevier B.V. All rights reserved.

Research progresses of SOI optical waveguide devices and integrated optical switch matrix

SOI (silicon-on-insulator) is a new material with a lot of important performances such as large index difference, low transmission loss. Fabrication processes for SOI based optoelectronic devices are compatible with conventional IC processes. Having the potential of OEIC monolithic integration, SOI based optoelectronic devices have shown many good characteristics and become more and more attractive recently. In this paper, the recent progresses of SOI waveguide devices in our research group are presented. By highly effective numerical simulation, the single mode conditions for SOI rib waveguides with rectangular and trapezoidal cross-section were accurately investigated. Using both chemical anisotropic wet etching and plasma dry etching techniques, SOI single mode rib waveguide, MMI coupler, VOA (variable optical attenuator), 2X2 thermal-optical switch were successfully designed and fabricated. Based on these, 4X4 and 8X8 SOI optical waveguide integrated switch matrixes are demonstrated for the first time.

Fabrication of arrayed waveguide grating based on SOI material

An arrayed waveguide grating based on SOI material was fabricated by inductive coupled plasma (ICP) etching technology. The central wavelength of the device was designed at 1.5509 mu m and the channel spacing was 200 GHz. Comparing with the values of the design, the differences of the central wavelength and the channel spacing in the test were 0.28 nm and 0.02 nm, respectively. The adjacent channel crosstalk was about 10 dB, and the uniformity of the five channels' insertion loss was only 0.7 dB. The results show that the device can be used as a demultiplexer.

Fabrication and analysis of 2x2 thermo-optic SOI waveguide switch with low power consumption and fast response by anisotropy chemical etching

A low power consumption 2 x 2 thermo-optic switch with fast response was fabricated on silicon-on-insulator by anisotropy chemical etching. Blocking trenches were etched on both sides of the phase-shifting arms to shorten device length and reduce power consumption. Thin top cladding layer was grown to reduce power consumption and switching time. The device showed good characteristics, including a low switching power of 145 mW and a fast switching speed of 8 +/- 1 mus, respectively. Two-dimensional finite element method was applied to simulate temperature field in the phase-shifting arm instead of conventional one-dimensional method. According to the simulated result, a new two-dimensional index distribution of phase-shifting arm was determined. Consequently finite-difference beam propagation method was employed to simulate the light propagation in the switch, and calculate the power consumption as well as the switching speed. The experimental results were in good agreement with the theoretical estimations. (C) 2004 Elsevier B.V. All rights reserved.

Effects of the technology of implanting nitrogen into buried oxide layer on the characteristics of partially depleted SOI nMOSFET

The effects, caused by the process of the implantation of nitrogen in the buried oxide layer of SIMOX wafer, on the characteristics of partially depleted silicon-on-insulator nMOSFET have been studied. The experimental results show that the channel electron mobilities of the devices fabricated on the SIMON (separation by implanted oxygen and nitrogen) wafers are lower than those of the devices made on the SIMOX (separation by implanted oxygen) wafers. The devices corresponding to the lowest implantation dose have the lowest mobility within the range of the implantation dose given in this paper. The value of the channel electron mobility rises slightly and tends to a limit when the implantation dose becomes greater. This is explained in terms of the rough Si/SiO2 interface due to the process of implantation of nitrogen. The increasing negative shifts of the threshold voltages for the devices fabricated on the SIMON wafers are also observed with the increase of implanting dose of nitrogen. However, for the devices fabricated on the SIMON wafers with the lowest dose of implanted nitrogen in this paper, their threshold voltages are slightly larger on the average than those prepared on the SIMOX wafers. The shifts are considered to be due to the increment of the fixed oxide charge in SiO2 layer and the change of the density of the interface-trapped charge with the value and distribution included. In particular, the devices fabricated on the SIMON wafers show a weakened kink effect, compared to the ones made on the SIMOX wafers.

Blind image restoration based on the theory of high-dimensional space geometry

In practical situations, the causes of image blurring are often undiscovered or difficult to get known. However, traditional methods usually assume the knowledge of the blur has been known prior to the restoring process, which are not practicable for blind image restoration. A new method proposed in this paper aims exactly at blind image restoration. The restoration process is transformed into a problem of point distribution analysis in high-dimensional space. Experiments have proved that the restoration could be achieved using this method without re-knowledge of the image blur. In addition, the algorithm guarantees to be convergent and has simple computation.

The image coding scheme based on neural network and SVM

This paper applies data coding thought, which based on the virtual information source modeling put forward by the author, to propose the image coding (compression) scheme based on neural network and SVM. This scheme is composed by "the image coding (compression) scheme based oil SVM" embedded "the lossless data compression scheme based oil neural network". The experiments show that the scheme has high compression ratio under the slightly damages condition, partly solve the contradiction which 'high fidelity' and 'high compression ratio' cannot unify in image coding system.