The use of Th in HTR: State of the art and implementation in Th/Pu fuel cycles

Nowadays nuclear is the only greenhouse-free source that can appreciably respond to the increasing worldwide energy demand. The use of Thorium in the nuclear energy production may offer some advantages to accomplish this task. Extensive R&D on the thorium fuel cycle has been conducted in many countries around the world. Starting from the current nuclear waste policy, the EU-PUMA project focuses on the potential benefits of using the HTR core as a Pu/MA transmuter. In this paper the following aspects have been analysed: (1) the state-of-the-art of the studies on the use of Th in different reactors, (2) the use of Th in HTRs, with a particular emphasis on Th-Pu fuel cycles, (3) an original assessment of Th-Pu fuel cycles in HTR. Some aspects related to Thorium exploitation were outlined, particularly its suitability for working in pebble-bed HTR in a Th-Pu fuel cycle. The influence of the Th/Pu weight fraction at BOC in a typical HTR pebble was analysed as far as the reactivity trend versus burn-up, the energy produced per Pu mass, and the Pu isotopic composition at EOC are concerned. Although deeper investigations need to be performed in order to draw final conclusions, it is possible to state that some optimized Th percentage in the initial Pu/Th fuel could be suggested on the basis of the aim we are trying to reach. Copyright © 2009 Guido Mazzini et al.

Implementation of shading effect for reconstruction of smooth layerbased 3D holographic images

A holographic rendering algorithm using a layer-based structure with angular tiling supports view-dependent shading and accommodation cues. This approach also has the advantages of rapid computation speed and visual reduction of layer gap artefacts compared to other approaches. Holograms rendered with this algorithm are displayed using an SLM to demonstrate view-dependent shading and occlusion. © 2013 SPIE-IS&T.

Implementation of trailer steering control on a multi-unit vehicle at high speeds

A high-speed path-following controller for long combination vehicles (LCVs) was designed and implemented on a test vehicle consisting of a rigid truck towing a dolly and a semitrailer. The vehicle was driven through a 3.5 m wide lane change maneuver at 80 km/h. The axles of the dolly and trailer were steered actively by electrically-controlled hydraulic actuators. Substantial performance benefits were recorded compared with the unsteered vehicle. For the best controller weightings, performance improvements relative to unsteered case were: lateral tracking error 75% reduction, rearward amplification (RA) of lateral acceleration 18% reduction, and RA of yaw rate 37% reduction. This represents a substantial improvement in stability margins. The system was found to work well in conjunction with the braking-based stability control system of the towing vehicle with no negative interaction effects being observed. In all cases, the stability control system and the steering system improved the yaw stability of the combination. © 2014 by ASME.

16 chip, 18 Gchips/s walsh-code implementation of an ECDMA access network using two time-shifted FIR filters

We demonstrate for the first time an electronically processed Walsh Code with 16 chips at 18Gchip/s. An auto-cross correlation ratio of 18.1dB is achieved between two orthogonal codes after transmission over 10km of SMF. © 2009 OSA.

Developing ISO 14649-based conversational programming system for multi-channel complex machine tools

A multi-channel complex machine tool (MCCM) is a versatile machining system equipped with more than two spindles and turrets for both turning and milling operations. Despite the potential of such a tool, the value of the hardware is largely dependent on how the machine tools are effectively programmed for machining. In this paper we consider a shop-floor programming system based on ISO 14649 (called e-CAM), the international standard for the interface between computer-aided manufacture (CAM) and computer numerical control (CNC). To be deployed in practical industrial usage a great deal of research has to be carried out. In this paper we present: 1) Design consideration for an e-CAM system, 2) The architecture design of e-CAM, 3) Major algorithms to fulfill the modules defined in the architecture, and 4) Implementation details.

System Dynamics and Scenario Planning: Implementation Challenges

In this paper we discuss key implementation challenges of a systems approach that combines System Dynamics, Scenario Planning and Qualitative Data Analysis methods in tackling a complex problem. We present the methods and the underlying framework. We then detail the main difficulties encountered in designing and planning the Scenario Planning workshop and how they were overcome, such as finding and involving the stakeholders and customising the process to fit within timing constraints. After presenting the results from this application, we argue that the consultants or system analysts need to engage with the stakeholders as process facilitators and not as system experts in order to gain commitment, trust and to improve information sharing. They also need be ready to adapt their tools and processes as well as their own thinking for more effective complex problem solving.

Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

function definition language fdl and its implementation

A Function Definition Language (FDL) is presented. Though designed for describing specifications, FDL is also a general-purpose functional programming language. It uses context-free language as data type, supports pattern matching definition of functions, offers several function definition forms, and is executable. It is shown that FDL has strong expressiveness, is easy to use and describes algorithms concisely and naturally. An interpreter of FDL is introduced. Experiments and discussion are included.