956 resultados para low voltage circuit breakers
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Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e Computadores
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Diplomityössä tavoitteena on etsiä teknistaloudellisimmat ratkaisut sekä tutkia niiden vaikutuksia sähkönjakeluverkoston käyttövarmuuteen ja luotettavuuteen toimitusvarmuuskriteeristön näkökulmasta. Lisäksi työssä esitetään uusi tunnusluku kriteeristön ylityksestä aiheutuvan haitan arvostukseen. Merkittävä osa Rovakaira Oy:n keskijänniteverkosta joudutaan uusimaan lähivuosikymmeninä teknistaloudellisen pitoajan täyttyessä. Verkon uusiminen antaa mahdollisuuden toteuttaa verkkoa nykyisiin vaatimuksiin paremmin sopivilla ratkaisuilla. Kehitysvaihtoehtoina vertaillaan johdon tien varteen siirtoa, maastokatkaisijoiden lisäämistä, pienitehoisten ja päättyvien haarajohtojen korvaamista 1 kV tekniikalla sekä pienoissähköaseman kannattavuutta. Työssä tarkastellaan yksityiskohtaisemmin Sodankylän käyttövarmuuden parantamista sähköasemavian aikana ja alueen kuormituksenkasvuun varautumista.
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A low-cost circuit was developed for stable and efficient maximum power point (MPP) tracking in autonomous photo voltaic-motor systems with variable-frequency drives (VFDs). The circuit is made of two resistors, two capacitors, and two Zener diodes. Its input is the photovoltaic (PV) array voltage and its output feeds the proportional-integral-derivative (PID) controller usually integrated into, the drive. The steady-state frequency-voltage oscillations induced by the circuit were treated in a simplified mathematical model, which was validated by widely characterizing a PV-powered centrifugal pump. General procedures for circuit and controller tuning were recommended based on model equations. The tracking circuit presented here is widely applicable to PV-motor system with VFDs, offering an. efficient open-access technology of unique simplicity. Copyright (C) 2010 John Wiley & Sons, Ltd.
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This paper provides a discussion on future direct current (DC) network development in terms of system protection under DC-side fault scenarios. The argument between appropriate DC circuit breaker and new DC fault-tolerant converters is discussed after a review on DC technology development and bottleneck issues that require proper solutions. The overcurrent/cost curve of power-electronic DC circuit breakers (CB) superimposed to voltage-source converter (VSC) systems is derived and compared with other possible fault-tolerant power conversion options. This in-advance planning of protection capability is essential for the future development of DC networks.
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This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data. This family of memories is characterized by a 3D structure to minimize the area penalty and to cope with latchups, as well as by the presence of integrated capacitors to hinder the occurrence of single event upsets. In low voltage static tests, classical single event upsets were a minor source of errors, but other unexpected phenomena such as clusters of bitflips and hard errors turned out to be the origin of hundreds of bitflips. Besides, errors were not observed in dynamic tests at nominal voltage. This behavior is clearly different than that of standard bulk CMOS SRAMs, where thousands of errors have been reported.
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This paper presents a robust voltage control scheme for fixed-speed wind generators using a static synchronous compensator (STATCOM) controller. To enable a linear and robust control framework with structured uncertainty, the overall system is represented by a linear part plus a nonlinear part that covers an operating range of interest required to ensure stability during severe low voltages. The proposed methodology is flexible and readily applicable to larger wind farms of different configurations. The performance of the control strategy is demonstrated on a two area test system. Large disturbance simulations demonstrate that the proposed controller enhances voltage stability as well as transient stability of induction generators during low voltage ride through (LVRT) transients and thus enhances the LVRT capability. (C) 2011 Elsevier Ltd. All rights reserved.
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In this work the performance of graded-channel (CC) SOI MOSFETs operating as source-follower buffers is presented. The experimental analysis is performed by comparing the gain and linearity of buffers implemented with CC and standard SOI MOS devices considering the same mask dimensions. It is shown that by using CC devices, buffer gain very close to the theoretical limit can be achieved, with improved linearity, while for standard devices the gain departs from the theoretical value depending on the inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to confirm some hypotheses proposed to explain the gain behavior observed in the experimental data. By using numerical simulations the channel length has been varied, showing that the gain of buffers implemented with CC devices remains close to the theoretical limit even when short-channel devices are adopted. It has also been shown that the length of a source-follower buffer using CC devices can be reduced by a factor of 5, in comparison with a standard Sol MOSFET, without gain loss or linearity degradation. (C) 2008 Elsevier Ltd. All rights reserved.
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Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35 mu m CMOS technology.
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Breast cancer is the most common type of cancer worldwide. The effectiveness of its treatment depends on early stage detection, as well as on the accuracy of its diagnosis. Recently, diagnosis techniques have been submitted to relevant breakthroughs with the upcoming of Magnetic Resonance Imaging, Ultrasound Sonograms and Positron Emission Tomography (PET) scans, among others. The work presented here is focused on studying the application of a PET system to a Positron Emission Mammography (PEM) system. A PET/PEM system works under the principle that a scintillating crystal will detect a gamma-ray pulse, originated at the cancerous cells, converting it into a correspondent visible light pulse. The latter must then be converted into an electrical current pulse by means of a Photo- -Sensitive Device (PSD). After the PSD there must be a Transimpedance Amplifier (TIA) in order to convert the current pulse into a suitable output voltage, in a time period lower than 40 ns. In this Thesis, the PSD considered is a Silicon Photo-Multiplier (SiPM). The usage of this recently developed type of PSD is impracticable with the conventional TIA topologies, as it will be proven. Therefore, the usage of the Regulated Common-Gate (RCG) topology will be studied in the design of the amplifier. There will be also presented two RCG variations, comprising a noise response improvement and differential operation of the circuit. The mentioned topology will also be tested in a Radio-Frequency front-end, showing the versatility of the RCG. A study comprising a low-voltage self-biasing feedback TIA will also be shown. The proposed circuits will be simulated with standard CMOS technology (UMC 130 nm), using a 1.2 V power supply. A power consumption of 0.34 mW with a signal-to-noise ratio of 43 dB was achieved.
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In this thesis a piezoelectric energy harvesting system, responsible for regulating the power output of a piezoelectric transducer subjected to ambient vibration, is designed to power an RF receiver with a 6 mW power consump-tion. The electrical characterisation of the chosen piezoelectric transducer is the starting point of the design, which subsequently presents a full-bridge cross-coupled rectifier that rectifies the AC output of the transducer and a low-dropout regulator responsible for delivering a constant voltage system output of 0.6 V, with low voltage ripple, which represents the receiver’s required sup-ply voltage. The circuit is designed using CMOS 130 nm UMC technology, and the system presents an inductorless architecture, with reduced area and cost. The electrical simulations run for the complete circuit lead to the conclusion that the proposed piezoelectric energy harvesting system is a plausible solution to power the RF receiver, provided that the chosen transducer is subjected to moderate levels of vibration.
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Nowadays it is necessary to research other types of energy alternatives and find the way to supply and save the energy we waste. The aim of the project consist of programming a microprocessor to measure if an oven radiates heat to the exterior, for the measure It is used a Peltier element that generates a voltage depending of the temperature difference between the oven and the air of the place where the oven is situated; The energy generated by the oven will be recollected in a condensor. A sensor will be used to know the exact measure. The second part of the project the main propose, is the development of a harvester. The microprocessor will use the voltage produced by the Peltier element to supply the electricity that it needs to work. A low power circuit and the appropriate software are needed to save the voltage generated.
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The aim of this work was to develop a low-cost circuit for real-time analog computation of the respiratory mechanical impedance in sleep studies. The practical performance of the circuit was tested in six patients with obstructive sleep apnea. The impedance signal provided by the analog circuit was compared with the impedance calculated simultaneously with a conventional computerized system. We concluded that the low-cost analog circuit developed could be a useful tool for facilitating the real-time assessment of airway obstruction in routine sleep studies.
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The aim of this work was to develop a low-cost circuit for real-time analog computation of the respiratory mechanical impedance in sleep studies. The practical performance of the circuit was tested in six patients with obstructive sleep apnea. The impedance signal provided by the analog circuit was compared with the impedance calculated simultaneously with a conventional computerized system. We concluded that the low-cost analog circuit developed could be a useful tool for facilitating the real-time assessment of airway obstruction in routine sleep studies.
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The supply voltage decrease and powerconsumption increase of modern ICs made the requirements for low voltage fluctuation caused by packaging and on-chip parasitic impedances more difficult to achieve. Most of the research works on the area assume that all the nodes of the chip are fed at thesame voltage, in such a way that the main cause of disturbance or fluctuation is the parasitic impedance of packaging. In the paper an approach to analyze the effect of high and fast current demands on the on-chip power supply network. First an approach to model the entire network by considering a homogeneous conductive foil is presented. The modification of the timing parameters of flipflops caused by spatial voltage drops through the IC surface are also investigated.
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Tämän diplomityön tarkoitus on selvittää pienjakelujännitteen nostosta aiheutuvia vaikutuksia sellutehtaan varavoimaverkossa. Työn alussa esitellään varavoimaverkkoon kuuluvia osia, selvitetään erilaisten kuormien vaikutusta varavoimaverkon sähkön laatuun sekä kuormien jakoa varmennettuihin verkkoihin. Seuraavaksi suunnitellaan kaksi keskitettyä varavoimaverkkomallia eri pienjakelujännitteillä. Mallien nimellisjännitteet ovat 400 V ja 690 V. Varavoimaverkkomallien kuormat ja osastojen väliset etäisyydet on otettu valmiista sellutehtaista. Tässä diplomityössä painotutaan erityisesti varavoimaverkkomallien mitoitukseen ja jakelujännitteen nostosta aiheutuvien vaikutusten teknistaloudelliseen vertailuun. Vertailu tehdään keskijännitekojeiston ja varavoimakeskusten välisellä alueella, johon kuu-luvat jakelumuuntaja, varavoimakone, varavoimapääkeskus, kiskosillat, jakelukaapelit, kytkinvaroke- ja katkaisijalähdöt sekä mahdolliset välimuuntajat. Varavoimaverkkojen välisessä kustannusvertailussa käytetään nykyarvomenetelmää.