981 resultados para annealing time
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Photoluminescence at room temperature in Ba(Zr0.25Ti0.75)O-3 thin films was explained by the degree of structural order-disorder. Ultraviolet-visible absorption spectroscopy, photoluminescence, and first principles quantum mechanical measurements were performed. The film annealed at 400 degrees C for 4 h presents intense visible photoluminescence behavior at room temperature. The increase of temperature and annealing time creates [ZrO6]-[TiO6] clusters in the lattice leading to the trapping of electrons and holes. Thus, [ZrO5]-[TiO6]/[ZrO6]-[TiO6] clusters were the main reason for the photoluminescence behavior.
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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
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Transparent glass ceramics have been prepared in the Ga2S3-GeS2-CsCI pseudoternary system appropriate heat treatment time and temperature. In situ X-ray diffraction at the heat treatment temperature and Cs-133 and Ga-71 solid-state nuclear magnetic resonance have been performed in function of annealing time to understand the crystallization process. Both techniques have evidenced the nucleating agent role played by gallium with the formation of Ga2S3 nanocrystals. on the other hand, cesium is incorporated very much later into the crystallites during the ceramization. Moreover, the addition of CsCl, which is readily integrated into the glassy network, permits us to shift the optical band gap toward shorter wavelength. Thus, new glass ceramics transmitting in the whole visible range up to 11.5 mu m have been Successfully synthesized from the (Ga2S3)(35)-(GeS2)(25)-CsCl40 base glass composition.
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Intense and broad photoluminescence (PL) emission at room temperature was observed on structurally disordered Ba[Zr0.25Ti0.75]O-3 (BZT) powders synthesized by the polymeric precursor method. BZT powders were annealed at 573 K for different times and at 973 K for 2 h in oxygen atmosphere. The single-phase cubic perovskite structure of the powder annealed at 973 K for 2 It was identified by X-ray diffraction and Fourier transform Raman techniques. PL emission increased with the increase of annealing time, which reached its maximum value in the powder annealed at 573 K for 192 h. First principles quantum mechanical calculations based on density functional theory (B3LYP level) were employed to study the electronic structure of ordered and disordered models. The theoretical calculations and experimental measurements of Ultraviolet-visible absorption spectroscopy indicate that the presence of intermediary energy levels in the band gap is favorable for the intense and broad PL emission at room temperature in disordered BZT powders. The PL behavior is probably due the existence of a charge gradient on the disordered structure, denoted by means of a charge transfer process from [TiO5]-[ZrO6] or [TiO6]-[ZrO5] clusters to [TiO6]-[ZrO6] clusters. (C) 2008 Elsevier Ltd. All rights reserved.
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Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
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Alumina thin films have been obtained by resistive evaporation of Al layer, followed by thermal oxidation by means of annealing in appropriate atmosphere (air or O2-rich), with variation of annealing time and temperature. Optical and structural properties of the investigated films reveal that the temperature of 550 °C is responsible for reasonable oxidation, which is accelerated up to 8 times for O2-rich atmosphere. Results of surface electrical resistivity and Raman spectroscopy are in good agreement with these findings. Surprisingly, X-ray and Raman data suggest also the crystallization of Si nuclei at glass substrate-alumina interface, which would come from the soda-lime glass used as substrate. © 2013 Elsevier Ltd and Techna Group S.r.l.
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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
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Alumina thin films have been obtained by resistive evaporation of Al layer, followed by thermal oxidation achieved by annealing in appropriate atmosphere (air or O-2-rich), with variation of annealing time and temperature. Optical and structural properties of the investigated films reveal that the temperature of 550 degrees C is responsible for fair oxidation. Results of surface electrical resistivity, Raman and infrared spectroscopies are in good agreement with this finding. X-ray and Raman data also suggest the crystallization of Si nuclei at glass substrate-alumina interface, which would come from the soda-lime glass used as substrate. The main goal in this work is the deposition of alumina on top of SnO2 to build a transparent field-effect transistor. Some microscopy results of the assembled SnO2/Al2O3 heterostructure are also shown.
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Alumina thin films have been obtained by resistive evaporation of Al layer, followed by thermal oxidation achieved by annealing in appropriate atmosphere (air or O2-rich), with variation of annealing time and temperature. Optical and structural properties of the investigated films reveal that the temperature of 550°C is responsible for fair oxidation. Results of surface electrical resistivity, Raman and infrared spectroscopies are in good agreement with this finding. X-ray and Raman data also suggest the crystallization of Si nuclei at glass substrate-alumina interface, which would come from the soda-lime glass used as substrate. The main goal in this work is the deposition of alumina on top of SnO2 to build a transparent field-effect transistor. Some microscopy results of the assembled SnO2/Al2O3 heterostructure are also shown.
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Using inert gas condensation techniques the properties of sputtered neodymium-iron-born clusters were investigated. A D.C. magnetron sputtering source created vaporous Nd-Fe-B which was then condensed into clusters and deposited onto silicon substrates. A composite target of Nd-Fe-B discs on an iron plate and a composite target of Nd-(Fe-Co)-B were utilized to create clusters. The clusters were coated with a carbon layer through R.F. sputtering to prevent oxidation. Samples were investigated in the TEM and showed a size distribution with an average particle diameter of 8.11 nm. The clusters, upon deposition, were amorphous as indicated by diffuse diffraction patterns obtained through SAD. The EDS showed compositionally a direct correlation in the ratio of rare-earth to transition metals between the target and deposited samples. The magnetic properties of the as-deposited clusters showed superparamagnetic properties at high temperatures and ferromagnetic properties at low temperatures; these properties are indicative of rare-earth transition metal amorphous clusters. Annealing of samples showed an initial increase in the coercivity. Samples were annealed in an inert gas atmosphere at 600o C for increasing amounts of time. The samples showed an initial increase in coercivity, but showed no additional increases with additional annealing time. SAD of annealed cluster samples showed the presence of Nd2Fe17 and a bcc-Nd phase. The bcc-Nd is the result of oxidation at high temperatures created during annealing and surface interface energy. The magnetic properties of the annealed samples showed weak coercivity and a saturation magnetization equivalent to that of Nd2Fe17. The annealed clusters showed a slight increase in coercivity at low temperatures. These results indicate a loss of boron during the sputtering process.
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In this paper, we report on luminescence and absorbance effects of Er+3:Au-doped tellurite glasses synthesized by a melting-quenching and heat treatment technique. After annealing times of 2.5, 5.0, 7.5, and 10.0 h, at 300 A degrees C, the gold nanoparticles (GNP) effects on the Er+3 are verified from luminescence spectra and the corresponding levels lifetime. The localized surface plasmon resonance around 800 nm produced a maximum fluorescence enhancement for the band ranging from 800 to 840 nm, corresponding to the transitions H-4(11/2) -> aEuro parts per thousand I-4(13/2) (805 nm) and S-4(3/2) -> aEuro parts per thousand I-4(13/2) (840 nm), with annealing time till 7.5 h. The measured lifetime of the levels H-4(11/2) and S-4(3/2) confirmed the lifetime reduction due to the energy transfer from the GNP to Er+3, causing an enhanced photon emission rate in these levels.
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The conversion of dissipated heat into electricity is the basic principle of thermoelectricity. In this context, half-Heusler (HH) compounds are promising thermoelectric (TE) materials for waste heat recovery. They meet all the requirements for commercial TE applications, ranging from good efficiencies via environmentally friendliness to being low cost materials. This work focused on the TE properties of Ti0.3Zr0.35Hf0.35NiSn-based HH materials. This compound undergoes an intrinsic phase separation into a Ti-poor and Ti-rich HH phase during a rapid solidification process. The resulting dendritic microstructure causes a drastic reduction of the thermal conductivity, leading to higher TE efficiencies in these materials. The TE properties and temperature dependence of the phase-separated Ti0.3Zr0.35Hf0.35NiSn compound were investigated. The TE properties can be adjusted depending on the annealing treatment. The extension of annealing time for 21 days at 1000 °C revealed a reduction of the thermal conductivity and thus an enhancement of the TE performance in this sample. An increase of annealing temperature caused a change of the phase fraction ratio in favor of the Ti-rich phase, leading to an improvement of the electronic properties. rnInspired by the TE properties of the Ti0.3Zr0.35Hf0.35NiSn HH compound, the performance of different n- and p-type materials, realized via site substitution with donor and acceptor elements was examined. The fabrication of a TE n- and p-type material pair based on one starting compound can guarantee similar TE and mechanical properties and is enormous beneficial for device engineering. As donor dopants V, Nb and Sb were tested. Depending on the lattice position small doping levels were sufficient to attain distinct improvement in their TE efficiency. Acceptor-induced doping with Sc, Y and Co caused a change in the transport behavior from n- to p- type conduction, revealing the highest Seebeck coefficients obtained in the MNiSn system. rnThen, the long-term stability of an exemplary n- and p-type HH compound was proven. Surprisingly, the dendritic microstructure can be maintained even after 500 cycles (1700 h) from 373 to 873 K. The TE performance of both n- and p-type materials showed no significant change under the long-term treatment, indicating the extraordinary temperature stability of these compounds. Furthermore both HH materials revealed similar temperature-dependence of their mechanical properties. This work demonstrates the excellent suitability of phase-separated HH materials for future TE applications in the moderate temperature range.rn
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The thermal annealing of amorphous tracks of nanometer-size diameter generated in lithium niobate (LiNbO3) by Bromine ions at 45 MeV, i.e., in the electronic stopping regime, has been investigated by RBS/C spectrometry in the temperature range from 250°C to 350°C. Relatively low fluences have been used (<1012 cm−2) to produce isolated tracks. However, the possible effect of track overlapping has been investigated by varying the fluence between 3×1011 cm−2 and 1012 cm−2. The annealing process follows a two-step kinetics. In a first stage (I) the track radius decreases linearly with the annealing time. It obeys an Arrhenius-type dependence on annealing temperature with activation energy around 1.5 eV. The second stage (II) operates after the track radius has decreased down to around 2.5 nm and shows a much lower radial velocity. The data for stage I appear consistent with a solid-phase epitaxial process that yields a constant recrystallization rate at the amorphous-crystalline boundary. HRTEM has been used to monitor the existence and the size of the annealed isolated tracks in the second stage. On the other hand, the thermal annealing of homogeneous (buried) amorphous layers has been investigated within the same temperature range, on samples irradiated with Fluorine at 20 MeV and fluences of ∼1014 cm−2. Optical techniques are very suitable for this case and have been used to monitor the recrystallization of the layers. The annealing process induces a displacement of the crystalline-amorphous boundary that is also linear with annealing time, and the recrystallization rates are consistent with those measured for tracks. The comparison of these data with those previously obtained for the heavily damaged (amorphous) layers produced by elastic nuclear collisions is summarily discussed.
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Los transistores de alta movilidad electrónica basados en GaN han sido objeto de una extensa investigación ya que tanto el GaN como sus aleaciones presentan unas excelentes propiedades eléctricas (alta movilidad, elevada concentración de portadores y campo eléctrico crítico alto). Aunque recientemente se han incluido en algunas aplicaciones comerciales, su expansión en el mercado está condicionada a la mejora de varios asuntos relacionados con su rendimiento y habilidad. Durante esta tesis se han abordado algunos de estos aspectos relevantes; por ejemplo, la fabricación de enhancement mode HEMTs, su funcionamiento a alta temperatura, el auto calentamiento y el atrapamiento de carga. Los HEMTs normalmente apagado o enhancement mode han atraído la atención de la comunidad científica dedicada al desarrollo de circuitos amplificadores y conmutadores de potencia, ya que su utilización disminuiría significativamente el consumo de potencia; además de requerir solamente una tensión de alimentación negativa, y reducir la complejidad del circuito y su coste. Durante esta tesis se han evaluado varias técnicas utilizadas para la fabricación de estos dispositivos: el ataque húmedo para conseguir el gate-recess en heterostructuras de InAl(Ga)N/GaN; y tratamientos basados en flúor (plasma CF4 e implantación de F) de la zona debajo de la puerta. Se han llevado a cabo ataques húmedos en heteroestructuras de InAl(Ga)N crecidas sobre sustratos de Si, SiC y zafiro. El ataque completo de la barrera se consiguió únicamente en las muestras con sustrato de Si. Por lo tanto, se puede deducir que la velocidad de ataque depende de la densidad de dislocaciones presentes en la estructura, ya que el Si presenta un peor ajuste del parámetro de red con el GaN. En relación a los tratamientos basados en flúor, se ha comprobado que es necesario realizar un recocido térmico después de la fabricación de la puerta para recuperar la heteroestructura de los daños causados durante dichos tratamientos. Además, el estudio de la evolución de la tensión umbral con el tiempo de recocido ha demostrado que en los HEMTs tratados con plasma ésta tiende a valores más negativos al aumentar el tiempo de recocido. Por el contrario, la tensión umbral de los HEMTs implantados se desplaza hacia valores más positivos, lo cual se atribuye a la introducción de iones de flúor a niveles más profundos de la heterostructura. Los transistores fabricados con plasma presentaron mejor funcionamiento en DC a temperatura ambiente que los implantados. Su estudio a alta temperatura ha revelado una reducción del funcionamiento de todos los dispositivos con la temperatura. Los valores iniciales de corriente de drenador y de transconductancia medidos a temperatura ambiente se recuperaron después del ciclo térmico, por lo que se deduce que dichos efectos térmicos son reversibles. Se han estudiado varios aspectos relacionados con el funcionamiento de los HEMTs a diferentes temperaturas. En primer lugar, se han evaluado las prestaciones de dispositivos de AlGaN/GaN sobre sustrato de Si con diferentes caps: GaN, in situ SiN e in situ SiN/GaN, desde 25 K hasta 550 K. Los transistores con in situ SiN presentaron los valores más altos de corriente drenador, transconductancia, y los valores más bajos de resistencia-ON, así como las mejores características en corte. Además, se ha confirmado que dichos dispositivos presentan gran robustez frente al estrés térmico. En segundo lugar, se ha estudiado el funcionamiento de transistores de InAlN/GaN con diferentes diseños y geometrías. Dichos dispositivos presentaron una reducción casi lineal de los parámetros en DC en el rango de temperaturas de 25°C hasta 225°C. Esto se debe principalmente a la dependencia térmica de la movilidad electrónica, y también a la reducción de la drift velocity con la temperatura. Además, los transistores con mayores longitudes de puerta mostraron una mayor reducción de su funcionamiento, lo cual se atribuye a que la drift velocity disminuye más considerablemente con la temperatura cuando el campo eléctrico es pequeño. De manera similar, al aumentar la distancia entre la puerta y el drenador, el funcionamiento del HEMT presentó una mayor reducción con la temperatura. Por lo tanto, se puede deducir que la degradación del funcionamiento de los HEMTs causada por el aumento de la temperatura depende tanto de la longitud de la puerta como de la distancia entre la puerta y el drenador. Por otra parte, la alta densidad de potencia generada en la región activa de estos transistores conlleva el auto calentamiento de los mismos por efecto Joule, lo cual puede degradar su funcionamiento y Habilidad. Durante esta tesis se ha desarrollado un simple método para la determinación de la temperatura del canal basado en medidas eléctricas. La aplicación de dicha técnica junto con la realización de simulaciones electrotérmicas han posibilitado el estudio de varios aspectos relacionados con el autocalentamiento. Por ejemplo, se han evaluado sus efectos en dispositivos sobre Si, SiC, y zafiro. Los transistores sobre SiC han mostrado menores efectos gracias a la mayor conductividad térmica del SiC, lo cual confirma el papel clave que desempeña el sustrato en el autocalentamiento. Se ha observado que la geometría del dispositivo tiene cierta influencia en dichos efectos, destacando que la distribución del calor generado en la zona del canal depende de la distancia entre la puerta y el drenador. Además, se ha demostrado que la temperatura ambiente tiene un considerable impacto en el autocalentamiento, lo que se atribuye principalmente a la dependencia térmica de la conductividad térmica de las capas y sustrato que forman la heterostructura. Por último, se han realizado numerosas medidas en pulsado para estudiar el atrapamiento de carga en HEMTs sobre sustratos de SiC con barreras de AlGaN y de InAlN. Los resultados obtenidos en los transistores con barrera de AlGaN han presentado una disminución de la corriente de drenador y de la transconductancia sin mostrar un cambio en la tensión umbral. Por lo tanto, se puede deducir que la posible localización de las trampas es la región de acceso entre la puerta y el drenador. Por el contrario, la reducción de la corriente de drenador observada en los dispositivos con barrera de InAlN llevaba asociado un cambio significativo en la tensión umbral, lo que implica la existencia de trampas situadas en la zona debajo de la puerta. Además, el significativo aumento del valor de la resistencia-ON y la degradación de la transconductancia revelan la presencia de trampas en la zona de acceso entre la puerta y el drenador. La evaluación de los efectos del atrapamiento de carga en dispositivos con diferentes geometrías ha demostrado que dichos efectos son menos notables en aquellos transistores con mayor longitud de puerta o mayor distancia entre puerta y drenador. Esta dependencia con la geometría se puede explicar considerando que la longitud y densidad de trampas de la puerta virtual son independientes de las dimensiones del dispositivo. Finalmente se puede deducir que para conseguir el diseño óptimo durante la fase de diseño no sólo hay que tener en cuenta la aplicación final sino también la influencia que tiene la geometría en los diferentes aspectos estudiados (funcionamiento a alta temperatura, autocalentamiento, y atrapamiento de carga). ABSTRACT GaN-based high electron mobility transistors have been under extensive research due to the excellent electrical properties of GaN and its related alloys (high carrier concentration, high mobility, and high critical electric field). Although these devices have been recently included in commercial applications, some performance and reliability issues need to be addressed for their expansion in the market. Some of these relevant aspects have been studied during this thesis; for instance, the fabrication of enhancement mode HEMTs, the device performance at high temperature, the self-heating and the charge trapping. Enhancement mode HEMTs have become more attractive mainly because their use leads to a significant reduction of the power consumption during the stand-by state. Moreover, they enable the fabrication of simpler power amplifier circuits and high-power switches because they allow the elimination of negativepolarity voltage supply, reducing significantly the circuit complexity and system cost. In this thesis, different techniques for the fabrication of these devices have been assessed: wet-etching for achieving the gate-recess in InAl(Ga)N/GaN devices and two different fluorine-based treatments (CF4 plasma and F implantation). Regarding the wet-etching, experiments have been carried out in InAl(Ga)N/GaN grown on different substrates: Si, sapphire, and SiC. The total recess of the barrier was achieved after 3 min of etching in devices grown on Si substrate. This suggests that the etch rate can critically depend on the dislocations present in the structure, since the Si exhibits the highest mismatch to GaN. Concerning the fluorine-based treatments, a post-gate thermal annealing was required to recover the damages caused to the structure during the fluorine-treatments. The study of the threshold voltage as a function of this annealing time has revealed that in the case of the plasma-treated devices it become more negative with the time increase. On the contrary, the threshold voltage of implanted HEMTs showed a positive shift when the annealing time was increased, which is attributed to the deep F implantation profile. Plasma-treated HEMTs have exhibited better DC performance at room temperature than the implanted devices. Their study at high temperature has revealed that their performance decreases with temperature. The initial performance measured at room temperature was recovered after the thermal cycle regardless of the fluorine treatment; therefore, the thermal effects were reversible. Thermal issues related to the device performance at different temperature have been addressed. Firstly, AlGaN/GaN HEMTs grown on Si substrate with different cap layers: GaN, in situ SiN, or in situ SiN/GaN, have been assessed from 25 K to 550 K. In situ SiN cap layer has been demonstrated to improve the device performance since HEMTs with this cap layer have exhibited the highest drain current and transconductance values, the lowest on-resistance, as well as the best off-state characteristics. Moreover, the evaluation of thermal stress impact on the device performance has confirmed the robustness of devices with in situ cap. Secondly, the high temperature performance of InAlN/GaN HEMTs with different layouts and geometries have been assessed. The devices under study have exhibited an almost linear reduction of the main DC parameters operating in a temperature range from room temperature to 225°C. This was mainly due to the thermal dependence of the electron mobility, and secondly to the drift velocity decrease with temperature. Moreover, HEMTs with large gate length values have exhibited a great reduction of the device performance. This was attributed to the greater decrease of the drift velocity for low electric fields. Similarly, the increase of the gate-to-drain distance led to a greater reduction of drain current and transconductance values. Therefore, this thermal performance degradation has been found to be dependent on both the gate length and the gate-to-drain distance. It was observed that the very high power density in the active region of these transistors leads to Joule self-heating, resulting in an increase of the device temperature, which can degrade the device performance and reliability. A simple electrical method have been developed during this work to determine the channel temperature. Furthermore, the application of this technique together with the performance of electro-thermal simulations have enabled the evaluation of different aspects related to the self-heating. For instance, the influence of the substrate have been confirmed by the study of devices grown on Si, SiC, and Sapphire. HEMTs grown on SiC substrate have been confirmed to exhibit the lowest self-heating effects thanks to its highest thermal conductivity. In addition to this, the distribution of the generated heat in the channel has been demonstrated to be dependent on the gate-to-drain distance. Besides the substrate and the geometry of the device, the ambient temperature has also been found to be relevant for the self-heating effects, mainly due to the temperature-dependent thermal conductivity of the layers and the substrate. Trapping effects have been evaluated by means of pulsed measurements in AlGaN and InAIN barrier devices. AlGaN barrier HEMTs have exhibited a de crease in drain current and transconductance without measurable threshold voltage change, suggesting the location of the traps in the gate-to-drain access region. On the contrary, InAIN barrier devices have showed a drain current associated with a positive shift of threshold voltage, which indicated that the traps were possibly located under the gate region. Moreover, a significant increase of the ON-resistance as well as a transconductance reduction were observed, revealing the presence of traps on the gate-drain access region. On the other hand, the assessment of devices with different geometries have demonstrated that the trapping effects are more noticeable in devices with either short gate length or the gate-to-drain distance. This can be attributed to the fact that the length and the trap density of the virtual gate are independent on the device geometry. Finally, it can be deduced that besides the final application requirements, the influence of the device geometry on the performance at high temperature, on the self-heating, as well as on the trapping effects need to be taken into account during the device design stage to achieve the optimal layout.