VLSI architecture of a K-best detector for MIMO--OFDM wireless communication systems

The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

风光互补发电系统的优化设计（I）CAD设计方法

给出了一整套利用CAD进行风光互补发电系统优化设计的方法。为了精确确定系统每小时的运行状态，采用了更精确地表征组件特性及评估实际获得的风光资源的数学模型。为了寻找出以最小设备投资成本满足用户用电要求的系统配置，首先在风力发电机容量固定不变的前提下，计算了与该容量风力发电机匹配的不同容量的PV方阵和蓄电池所组成的风／光／蓄组合的全年功率供给亏欠率LPSP，根据总的设备投资成本最小化的原则筛选出一组与该容量风力发电机对应的满足用户给定系统供电可靠性即LPSP值的风／光／蓄组合；然后通过改变风力发电机的容量，优选出多个与不同容量风力发电机对应的既能满足用户用电要求同时总的设备购置成本又是最低的风／光／蓄组合，比较它们的成本最终唯一确定出以最小投资成本满足用户用电要求的优化的系统配置。

一种通用神经网络处理机设计及其VLSI集成化讨论

于2010-11-23批量导入

CAD/RP系统间数据模型的转换方法与发展

分析了当前 CAD和 RP系统间数据模型的各种转换方法，并指明了进一步的发展方向。 STL交换标准的局限和不足已日趋明显，由 CAD模型直接分层得到的 CLI格式将成为与 STL文件并存的一种接口格式。

CAD/CAM一体化的应用与开发

文章概要地介绍了CAD/CAM系统的结构、CAD/CAM一体化的工作流程,提出实现CAD/CAM一体化的几种可行方案,并以具体零件机床为例,给出从设计到数控编程和机床加工的全过程。

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2007

An Analog VLSI Chip for Estimating the Focus of Expansion

For applications involving the control of moving vehicles, the recovery of relative motion between a camera and its environment is of high utility. This thesis describes the design and testing of a real-time analog VLSI chip which estimates the focus of expansion (FOE) from measured time-varying images. Our approach assumes a camera moving through a fixed world with translational velocity; the FOE is the projection of the translation vector onto the image plane. This location is the point towards which the camera is moving, and other points appear to be expanding outward from. By way of the camera imaging parameters, the location of the FOE gives the direction of 3-D translation. The algorithm we use for estimating the FOE minimizes the sum of squares of the differences at every pixel between the observed time variation of brightness and the predicted variation given the assumed position of the FOE. This minimization is not straightforward, because the relationship between the brightness derivatives depends on the unknown distance to the surface being imaged. However, image points where brightness is instantaneously constant play a critical role. Ideally, the FOE would be at the intersection of the tangents to the iso-brightness contours at these "stationary" points. In practice, brightness derivatives are hard to estimate accurately given that the image is quite noisy. Reliable results can nevertheless be obtained if the image contains many stationary points and the point is found that minimizes the sum of squares of the perpendicular distances from the tangents at the stationary points. The FOE chip calculates the gradient of this least-squares minimization sum, and the estimation is performed by closing a feedback loop around it. The chip has been implemented using an embedded CCD imager for image acquisition and a row-parallel processing scheme. A 64 x 64 version was fabricated in a 2um CCD/ BiCMOS process through MOSIS with a design goal of 200 mW of on-chip power, a top frame rate of 1000 frames/second, and a basic accuracy of 5%. A complete experimental system which estimates the FOE in real time using real motion and image scenes is demonstrated.

Computing 3-D Motion in Custom Analog and Digital VLSI

This thesis examines a complete design framework for a real-time, autonomous system with specialized VLSI hardware for computing 3-D camera motion. In the proposed architecture, the first step is to determine point correspondences between two images. Two processors, a CCD array edge detector and a mixed analog/digital binary block correlator, are proposed for this task. The report is divided into three parts. Part I covers the algorithmic analysis; part II describes the design and test of a 32$\time $32 CCD edge detector fabricated through MOSIS; and part III compares the design of the mixed analog/digital correlator to a fully digital implementation.

Slicing issues in CAD translation to STL in rapid prototyping

The rapid prototyping (RP) process is being used widely with great potential for rapid manufacturing of functional parts. The RP process involves translation of the CAD file to STL format followed by slicing of the model into multiple horizontal layers, each of which is reproduced physically in making the prototype. The thickness of the resulting slices has a profound effect on the surface finish and build time of the prototype. The purpose of this paper is to show the effects of slice thickness on the surface finish, layering error, and build time of a prototype, as well as to show how an efficient STL file can be developed. Three objects were modeled and STL files were generated. One STL file for each object was sliced using different slice thicknesses, and the build times were obtained. Screenshots were used to show the slicing effect on layering error and surface finish and to demonstrate the means to a more efficient STL file. From the results, it is clear that the surface finish and build time are important factors that are affected by slice thickness