High-Performance Sensors Based on Resistance Fluctuations of Single-Layer-Graphene Transistors

One of the most interesting predicted applications of graphenemonolayer-based devices is as high-quality sensors. In this article, we show, through systematic experiments, a chemical vapor sensor based on the measurement of lowfrequency resistance fluctuations of single-layer-graphene field-effect-transistor devices. The sensor has extremely high sensitivity, very high specificity, high fidelity, and fast response times. The performance of the device using this scheme of measurement (which uses resistance fluctuations as the detection parameter) is more than 2 orders of magnitude better than a detection scheme in which changes in the average value of the resistance is monitored. We propose a number-densityfluctuation-based model to explain the superior characteristics of a noisemeasurement-based detection scheme presented in this article.

Percolative switching in transition metal dichalcogenide field-effect transistors at room temperature

We have addressed the microscopic transport mechanism at the switching or `on-off' transition in transition metal dichalcogenide (TMDC) field-effect transistors (FETs), which has been a controversial topic in TMDC electronics, especially at room temperature. With simultaneous measurement of channel conductivity and its slow time-dependent fluctuation (or noise) in ultrathin WSe2 and MoS2 FETs on insulating SiO2 substrates where noise arises from McWhorter-type carrier number fluctuations, we establish that the switching in conventional backgated TMDC FETs is a classical percolation transition in a medium of inhomogeneous carrier density distribution. From the experimentally observed exponents in the scaling of noise magnitude with conductivity, we observe unambiguous signatures of percolation in a random resistor network, particularly, in WSe2 FETs close to switching, which crosses over to continuum percolation at a higher doping level. We demonstrate a powerful experimental probe to the microscopic nature of near-threshold electrical transport in TMDC FETs, irrespective of the material detail, device geometry, or carrier mobility, which can be extended to other classes of 2D material-based devices as well.

On the Geometrically Dependent Quasi-Saturation and g(m) Reduction in Advanced DeMOS Transistors

This paper reveals an early quasi-saturation (QS) effect attributed to the geometrical parameters in shallow trench isolation-type drain-extended MOS (STI-DeMOS) transistors in advanced CMOS technologies. The quasi-saturation effect leads to serious g(m) reduction in STI-DeMOS. This paper investigates the nonlinear resistive behavior of the drain-extended region and its impact on the particular behavior of the STI-DeMOS transistor. In difference to vertical DMOS or lateral DMOS structures, STI-DeMOS exhibits three distinct regions of the drain extension. A complete understanding of the physics in these regions and their impact on the QS behavior are developed in this paper. An optimization strategy is shown for an improved g(m) device in a state-of-the-art 28-nm CMOS technology node.

Design Optimization of Thin-Film Transistors Based on a Metal-Substrate-Semiconductor Architecture for High DC Voltage Sensing

We discuss the potential application of high dc voltage sensing using thin-film transistors (TFTs) on flexible substrates. High voltage sensing has potential applications for power transmission instrumentation. For this, we consider a gate metal-substrate-semiconductor architecture for TFTs. In this architecture, the flexible substrate not only provides mechanical support but also plays the role of the gate dielectric of the TFT. Hence, the thickness of the substrate needs to be optimized for maximizing transconductance, minimizing mechanical stress, and minimizing gate leakage currents. We discuss this optimization, and develop n-type and p-type organic TFTs using polyvinyldene fluoride as the substrate-gate insulator. Circuits are also realized to achieve level shifting, amplification, and high drain voltage operation.

Ink-jet printing of carbon nanotube thin film transistors

Ink-jet printing is an important process for placing active electronics on plastic substrates. We demonstrate ink-jet printing as a viable method for large area fabrication of carbon nanotube (CNT) thin film transistors (TFTs). We investigate different routes for producing stable CNT solutions ("inks"). These consist of dispersion methods for CNT debundling and the use of different solvents, such as N -methyl-2-pyrrolidone. The resulting printable inks are dispensed by ink-jet onto electrode bearing silicon substrates. The source to drain electrode gap is bridged by percolating networks of CNTs. Despite the presence of metallic CNTs, our devices exhibit field effect behavior, with effective mobility of ∼0.07 cm2 /V s and ON/OFF current ratio of up to 100. This result demonstrates the feasibility of ink-jet printing of nanostructured materials for TFT manufacture. © 2007 American Institute of Physics.

High performance nanocomposite thin film transistors with bilayer carbon nanotube-polythiophene active channel by ink-jet printing

Nanocomposite thin film transistors (TFTs) based on nonpercolating networks of single-walled carbon nanotubes (CNTs) and polythiophene semiconductor [poly [5, 5′ -bis(3-dodecyl-2-thienyl)- 2, 2′ -bithiophene] (PQT-12)] thin film hosts are demonstrated by ink-jet printing. A systematic study on the effect of CNT loading on the transistor performance and channel morphology is conducted. With an appropriate loading of CNTs into the active channel, ink-jet printed composite transistors show an effective hole mobility of 0.23 cm 2 V-1 s-1, which is an enhancement of more than a factor of 7 over ink-jet printed pristine PQT-12 TFTs. In addition, these devices display reasonable on/off current ratio of 105-10 6, low off currents of the order of 10 pA, and a sharp subthreshold slope (<0.8 V dec-1). The work presented here furthers our understanding of the interaction between polythiophene polymers and nonpercolating CNTs, where the CNT density in the bilayer structure substantially influences the morphology and transistor performance of polythiophene. Therefore, optimized loading of ink-jet printed CNTs is crucial to achieve device performance enhancement. High performance ink-jet printed nanocomposite TFTs can present a promising alternative to organic TFTs in printed electronic applications, including displays, sensors, radio-frequency identification (RFID) tags, and disposable electronics. © 2009 American Institute of Physics.

Zinc oxide nanostructures and high electron mobility nanocomposite thin film transistors

This paper reports on the synthesis of zinc oxide (ZnO) nanostructures and examines the performance of nanocomposite thin-film transistors (TFTs) fabricated using ZnO dispersed in both n- and p-type polymer host matrices. The ZnO nanostructures considered here comprise nanowires and tetrapods and were synthesized using vapor phase deposition techniques involving the carbothermal reduction of solid-phase zinc-containing compounds. Measurement results of nanocomposite TFTs based on dispersion of ZnO nanorods in an n-type organic semiconductor ([6, 6]-phenyl-C61-butyric acid methyl ester) show electron field-effect mobilities in the range 0.3-0.6 cm2V-1 s-1. representing an approximate enhancement by as much as a factor of 40 from the pristine state. The on/off current ratio of the nanocomposite TFTs approach 106 at saturation with off-currents on the order of 10 pA. The results presented here, although preliminary, show a highly promising enhancement for realization of high-performance solution-processable n-type organic TFTs. © 2008 IEEE.

Formation of composite organic thin film transistors with nanotubes and nanowires

Plastic electronics is a rapidly expanding topic, much of which has been focused on organic semiconductors. However, it is also of interest to find viable ways to integrate nanomaterials, such as silicon nanowires (SiNWs) and carbon nanotubes (CNTs), into this technology. Here, we present methods of fabrication of composite devices incorporating such nanostructured materials into an organic matrix. We investigate the formation of polymer/CNT composites, for which we use the semiconducting polymer poly(3,3‴-dialkyl-quaterthiophene) (PQT). We also report a method of fabricating polymer/SiNW TFTs, whereby sparse arrays of parallel oriented SiNWs are initially prepared on silicon dioxide substrates from forests of as-grown gold-catalysed SiNWs. Subsequent ink-jet printing of PQT on these arrays produces a polymer/SiNW composite film. We also present the electrical characterization of all composite devices. © 2007 Elsevier B.V. All rights reserved.

Semi-insulating layer for novel high voltage polysilicon thin film transistors

This work describes the deposition and characterisation of semi-insulating oxygen-doped silicon films for the development of high voltage polycrystalline silicon (poly-Si) circuitry on glass. The performance of a novel poly-Si High Voltage Thin Film Transistor (HVTFT) structure, incorporating a layer of semi-insulating material, has been investigated using a two dimensional device simulator. The semi-insulating layer increases the operating voltage of the HVTFT structure by linearising the potential distribution in the device offset region. A glass compatible semi-insulating layer, suitable for HVTFT applications, has been deposited by the Plasma Enhanced Chemical Vapour Deposition (PECVD) technique from silane (SiH4), nitrous oxide (N2O) and helium (He) gas mixtures. The as-deposited films are furnace annealed at 600°C which is the maximum process temperature. By varying the N2O/SiH4 ratio the conductivity of the annealed films can be accurately controlled up to a maximum of around 10-7 Ω-1cm-1. Helium dilution of the reactant gases improves both film uniformity and reproducibility. Raman analysis shows the as-deposited and annealed films to be completely amorphous. A model for the microstructure of these Semi-Insulating Amorphous Oxygen-Doped Silicon (SIAOS) films is proposed to explain the observed physical and electrical properties.

Persistent photoconductivity in Hf-In-Zn-O thin film transistors

Passivated Hf-In-Zn-O (HIZO) thin film transistors suffer from a negative threshold voltage shift under visible light stress due to persistent photoconductivity (PPC). Ionization of oxygen vacancy sites is identified as the origin of the PPC following observations of its temperature- and wavelength-dependence. This is further corroborated by the photoluminescence spectrum of the HIZO. We also show that the gate voltage can control the decay of PPC in the dark, giving rise to a memory action. © 2010 American Institute of Physics.

Instability in threshold voltage and subthreshold behavior in Hf-In-Zn-O thin film transistors induced by bias-and light-stress

Electrical bias and light stressing followed by natural recovery of amorphous hafnium-indium-zinc-oxide (HIZO) thin film transistors with a silicon oxide/nitride dielectric stack reveals defect density changes, charge trapping and persistent photoconductivity (PPC). In the absence of light, the polarity of bias stress controls the magnitude and direction of the threshold voltage shift (Δ VT), while under light stress, VT consistently shifts negatively. In all cases, there was no significant change in field-effect mobility. Light stress gives rise to a PPC with wavelength-dependent recovery on time scale of days. We observe that the PPC becomes more pronounced at shorter wavelengths. © 2010 American Institute of Physics.

Advantages of top-gate, high-k dielectric carbon nanotube field-effect transistors

The subthreshold slope, transconductance, threshold voltage, and hysteresis of a carbon nanotube field-effect transistor (CNT FET) were examined as its configuration was changed from bottom-gate exposed channel, bottom-gate covered channel to top-gate FET. An individual single wall CNT was grown by chemical vapor deposition and its gate configuration was changed while determining its transistor characteristics to ensure that the measurements were not a function of different chirality or diameter CNTs. The bottom-gate exposed CNT FET utilized 900 nm SiO2 as the gate insulator. This CNT FET was then covered with TiO2 to form the bottom-gate covered channel CNT FET. Finally, the top-gate CNT FET was fabricated and the device utilized TiO 2 (K ∼ 80, equivalent oxide thickness=0.25 nm) as the gate insulator. Of the three configurations investigated, the top-gate device exhibited best subthreshold slope (67-70 mV/dec), highest transconductance (1.3 μS), and negligible hysteresis in terms of threshold voltage shift. © 2006 American Institute of Physics.