Electroluminescence from GaN-polymer heterojunction

Inorganic and organic semiconductor devices are generally viewed as distinct and separate technologies. Herein we report a hybrid inorganic-organic light-emitting device employing the use of an air stable polymer, Poly (9,9-dioctylfluorene-alt-benzothiadiazole) as a p-type layer to create a heterojunction, avoiding the use of p-type GaN, which is difficult to grow, being prone to the complex and expensive fabrication techniques that characterises it. I-V characteristics of the GaN-polymer heterojunction fabricated by us exhibits excellent rectification. The luminescence onset voltage is typically about 8-10 V. The device emits yellowish white electroluminescence with CIE coordinates (0.42, 0.44). (C) 2011 Elsevier B.V. All rights reserved.

Performance Enhancement of the Tunnel Field Effect Transistor using SiGe Source

Due to extremely low off state current (IOFF) and excellent sub-threshold characteristics, the tunnel field effect transistor (TFET) has attracted a lot of attention for low standby power applications. In this work, we aim to increase the on state current (ION) of the device. A novel device architecture with a SiGe source is proposed. The proposed structure shows an order of improvement in ION compared to the conventional Si structure. A process flow adaptable to conventional CMOS technology is also addressed.

Composite instantaneous comparators basis for design and their transient performance

Principles of design of composite instantaneous comparators (a combination of amplitude- and phase- comparison techniques) are laid out to provide directional, directional-reactance, nonoffset-resistance and conductance characteristices. The respective signals provided by the voltage transformer and the current transformer are directly used as relaying signals without resorting to any form of mixing. Phase shifts required, are obtained by using magnetic ferrite cores in a novel manner. Sampling units employing a combination of ferrite cores and semiconductor devices provide highly reliable designs. Special attention is paid to the choice of relaying signals, to eliminate the need for any synchronisation or modification and to avoid `image¿ characteristics. These factors have resulted in a considerable simplification of the practical circuitry. A thyristor AND circuit is employed in dual comparator units to provide the final tripping, and leads to a circuit which is much less sensitive to extraneous signals than a single-thyristor unit.

Three-system and single-system static distance relays

Static distance relays employing semiconductor devices as their active elements offer many advantages over the conventional electromagnetic and rectifier relays. The paper describes single-system and three-system static distance relays, which depend for their operation on the instantaneous-comparison or `block-spike¿ scheme. Design principles and typical discriminating and logic circuits are described for the new relaying equipment. The relaying circuitry has been devised for obtaining uniform performance on all kinds of faults, by the use of two phase detectors¿one for multiphase faults and one for earth faults. The phase detector for multiphase faults provides an improved polar characteristic in the complex-impedance plane, which fits only around the fault area of a transmission line. The other features of the relay are: reliable pickup for close-in faults, least susceptibility to maloperation under power-swing conditions, and reduction in cost and panel space required. The operating characteristics of the relays, as expressed by accuracy/range charts, are also presented.

Digital Dead Time Logic and Protection Circuitry for PWM Voltage Source Converters

Power semiconductor devices have finite turn on and turn off delays that may not be perfectly matched. In a leg of a voltage source converter, the simultaneous turn on of one device and the turn off of the complementary device will cause a DC bus shoot through, if the turn off delay is larger than the turn on delay time. To avoid this situation it is common practice to blank the two complementary devices in a leg for a small duration of time while switching, which is called dead time. This paper proposes a logic circuit for digital implementation required to control the complementary devices of a leg independently and at the same time preventing cross conduction of devices in a leg, and while providing accurate and stable dead time. This implementation is based on the concept of finite state machines. This circuit can also block improper PWM pulses to semiconductor switches and filters small pulses notches below a threshold time width as the narrow pulses do not provide any significant contribution to average pole voltage, but leads to increased switching loss. This proposed dead time logic has been implemented in a CPLD and is implemented in a protection and delay card for 3- power converters.

Gate Drive Card for High Power Three Phase PWM Converters

Gate driver is an integral part of every power converter, drives the power semiconductor devices and also provides protection for the switches against short-circuit events and over-voltages during shut down. Gate drive card for IGBTs and MOSFETs with basic features can be designed easily by making use of discrete electronic components. Gate driver ICs provides attractive features in a single package, which improves reliability and reduces effort of design engineers. Either case needs one or more isolated power supplies to drive each power semiconductor devices and provide isolation to the control circuitry from the power circuit. The primary emphasis is then to provide simplified and compact isolated power supplies to the gate drive card with the requisite isolation strength and which consumes less space, and for providing thermal protection to the power semiconductor modules for 3-� 3 wire or 4 wire inverters.

Growth of InSb(1-x)Bix crystals by Rotatary Bridgman method and their characterization

The Rotatary Bridgman method was used to grow ternary InSb(1-x)SBix, crystals. In this method the ampoule was subjected to reversible rotation at a rate of 60rpm. High quality crystals of 8mm diameter and 25mm length were grown with 6.5 atomic percentage of Bi. The grown crystals were characterized employing various techniques such as energy dispersive spectroscopy, x-ray diffraction, differential scanning calorimetery, infrared spectroscopy and Hall measurement.

Graphene transistors for CMOS applications: opportunities and challenges

In the last decade, there has been a tremendous interest in Graphene transistors. The greatest advantage for CMOS nanoelectronics applications is the fact that Graphene is compatible with planar CMOS technology and potentially offers excellent short channel properties. Because of the zero bandgap, it will not be possible to turn off the MOSFET efficiently and hence the typical on current to off current ratio (Ion/Ioff) has been less than 10. Several techniques have been proposed to open the bandgap in Graphene. It has been demonstrated, both theoretically and experimentally, that Graphene Nanoribbons (GNR) show a bandgap which is inversely proportional to their width. GNRs with about 20 nm width have bandgaps in the range of 100meV. But it is very difficult to obtain GNRs with well defined edges. An alternate technique to open the band gap is to use bilayer Graphene (BLG), with an asymmetric bias applied in the direction perpendicular to their plane. Another important CMOS metric, the subthreshold slope is also limited by the inability to turn off the transistor. However, these devices could be attractive for RF CMOS applications. But even for analog and RF applications the non-saturating behavior of the drain current can be an issue. Although some studies have reported current saturation, the mechanisms are still not very clear. In this talk we present some of our recent findings, based on simulations and experiments, and propose possible solutions to obtain high on current to off current ratio. A detailed study on high field transport in grapheme transistors, relevant for analog and RF applications will also be presented.

Device oriented statistical modeling method for process variability in 45nm analog CMOS technology

With the rapid scaling down of the semiconductor process technology, the process variation aware circuit design has become essential today. Several statistical models have been proposed to deal with the process variation. We propose an accurate BSIM model for handling variability in 45nm CMOS technology. The MOSFET is designed to meet the specification of low standby power technology of International Technology Roadmap for Semiconductors (ITRS).The process parameters variation of annealing temperature, oxide thickness, halo dose and title angle of halo implant are considered for the model development. One parameter variation at a time is considered for developing the model. The model validation is done by performance matching with device simulation results and reported error is less than 10%.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

Wurtzite InN nanodots on Si(100) by molecular beam epitaxy

Studies were carried on the growth behavior of InN nanodots by plasma assisted molecular beam epitaxy on bare Si(100) substrates and their structural, optical, electrical properties. The growth was carried out by two different methods such as, (i) mono-step growth process at a low temperature and a (ii) bi-step growth process with the combination of low and high temperatures for the formation of single crystalline nanodots with well defined crystallographic facets due to cluster migration. Low temperature photoluminescence shows a free excitonic (FE) luminescence at 0.80 eV. The Raman spectroscopy and X-ray diffraction studies reveal that the nanodots as well as the film were of wurtzite structure and strain free.

Tuning the photoluminescence of ZnO thin films by indium doping

Zinc Oxide (ZnO) and indium doped ZnO (IZO) thin films with different indium compositions were grown on p-type boron doped Si substrates by pulsed laser deposition (PLD). The effect of indium concentration on the structural, optical and electrical properties of the film was studied. XRD, XPS and Raman studies confirm the single phase formation and successful doping of In in to ZnO. We observed various photoluminescence emissions, ranging from UV to visible, with the incorporation of In into ZnO. Room temperature Current-Voltage (I-V) characteristics showed good p-n junction properties for n-type-undoped and In doped ZnO with p-type substrates. The turn on voltage was observed to be decreasing with increase in In composition.

Growth and properties of nonpolar a-plane GaN grown on r-sapphire by plasma assisted molecular beam epitaxy

The growth of nonpolar a- plane (1 1 -2 0) orientation of the GaN epilayers were confirmed by high resolution x-ray diffraction studies. An in-plane orientation relationship was found to be 0 0 0 1] GaN parallel to -1 1 0 1] sapphire and -1 1 0 0] GaN parallel to 1 1 -2 0] sapphire. SEM image shows the reasonably smooth surface. The photoluminescence spectrum shows near band emission (NBE) at 3.439 eV. The room temperature I-V characteristics of Au/a-GaN schottky diode performed. The Schottky barrier height (phi(b)) and the ideality factor (eta) for the Au/a-GaN schottky diode found to be 0.50 eV and 2.01 respectively.