Architecture of Run-time Reconfigurable Channel Decoder

Modern wireline and wireless communication devices are multimode and multifunctional communication devices. In order to support multiple standards on a single platform, it is necessary to develop a reconfigurable architecture that can provide the required flexibility and performance. The Channel decoder is one of the most compute intensive and essential elements of any communication system. Most of the standards require a reconfigurable Channel decoder that is capable of performing Viterbi decoding and Turbo decoding. Furthermore, the Channel decoder needs to support different configurations of Viterbi and Turbo decoders. In this paper, we propose a reconfigurable Channel decoder that can be reconfigured for standards such as WCDMA, CDMA2000, IEEE802.11, DAB, DVB and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. A multiprocessor approach has been followed to provide higher throughput and scalable power consumption in various configurations of the reconfigurable Viterbi decoder and Turbo decoder. We have proposed A Hybrid register exchange approach for multiprocessor architecture to minimize power consumption.

Coplanar Capacitively Coupled Probe Fed Microstrip Antennas for Wideband Applications

The design and analysis of a coplanar capacitive fed microstrip antenna suspended above the ground plane is presented. It is demonstrated that the proposed approach can be used for designing antennas with impedance bandwidth of about 50% and a good gain to operate in various microwave bands. The model of the antenna incorporates the capacitive feed strip which is fed by a coaxial probe using equivalent circuit approach, and matches simulation and experimental results. The capacitive feed strip used here is basically a rectangular microstrip capacitor formed from a truncated microstrip transmission line and all its open ends are represented by terminal or edge capacitances. The error analysis was carried out for validity of the model for different design parameters. The antenna configuration can be used where unidirectional radiation patterns are required over a wide bandwidth.

Experimental investigation of three-layer electromagnetically coupled circular microstrip antennas

The broadband behaviour of a three-layer electromagnetically coupled circular microstrip antenna is investigated experimentally. The effects of interlayer spacings and the thickness of the parasitic layers on the impedance bandwidth, 3 dB beamwidth and pattern shape, are studied. Experiments show that this structure can provide a frequency bandwidth as high as 20% with a low crosspolarisation level and a moderately high gain.

A geodesic constant method for computing high-frequency mutual coupling between antennas on general quadric cylinders

A Geodesic Constant Method (GCM) is outlined which provides a common approach to ray tracing on quadric cylinders in general, and yields all the surface ray-geometric parameters required in the UTD mutual coupling analysis of conformal antenna arrays in the closed form. The approach permits the incorporation of a shaping parameter which permits the modeling of quadric cylindrical surfaces of desired sharpness/flatness with a common set of equations. The mutual admittance between the slots on a general parabolic cylinder is obtained as an illustration of the applicability of the GCM.

Resistivity imaging of a reconfigurable phantom with circular inhomogeneities in 2D-electrical impedance tomography

Resistivity imaging of a reconfigurable phantom with circular inhomogeneities is studied with a simple instrumentation and data acquisition system for Electrical Impedance Tomography. The reconfigurable phantom is developed with stainless steel electrodes and a sinusoidal current of constant amplitude is injected to the phantom boundary using opposite current injection protocol. Nylon and polypropylene cylinders with different cross sectional areas are kept inside the phantom and the boundary potential data are collected. The instrumentation and the data acquisition system with a DIP switch-based multiplexer board are used to inject a constant current of desired amplitude and frequency. Voltage data for the first eight current patterns (128 voltage data) are found to be sufficient to reconstruct the inhomogeneities and hence the acquisition time is reduced. Resistivity images are reconstructed from the boundary data for different inhomogeneity positions using EIDORS-2D. The results show that the shape and resistivity of the inhomogeneity as well as the background resistivity are successfully reconstructed from the potential data for single or double inhomogeneity phantoms. The resistivity images obtained from the single and double inhomogeneity phantom clearly indicate the inhomogeneity as the high resistive material. Contrast to noise ratio (CNR) and contrast recovery (CR) of the reconstructed images are found high for the inhomogeneities near all the electrodes arbitrarily chosen for the entire study. (C) 2010 Elsevier Ltd. All rights reserved.

Fast algorithm for data exchange in reconfigurable tree structures

This paper presents a fast algorithm for data exchange in a network of processors organized as a reconfigurable tree structure. For a given data exchange table, the algorithm generates a sequence of tree configurations in which the data exchanges are to be executed. A significant feature of the algorithm is that each exchange is executed in a tree configuration in which the source and destination nodes are adjacent to each other. It has been proved in a theorem that for every pair of nodes in the reconfigurable tree structure, there always exists two and only two configurations in which these two nodes are adjacent to each other. The algorithm utilizes this fact and determines the solution so as to optimize both the number of configurations required and the time to perform the data exchanges. Analysis of the algorithm shows that it has linear time complexity, and provides a large reduction in run-time as compared to a previously proposed algorithm. This is well-confirmed from the experimental results obtained by executing a large number of randomly-generated data exchange tables. Another significant feature of the algorithm is that the bit-size of the routing information code is always two bits, irrespective of the number of nodes in the tree. This not only increases the speed of the algorithm but also results in simpler hardware inside each node.

Quasi-Orthogonal Design and Performance Analysis of Amplify-And-Forward Relay Networks with Multiple-Antennas

This paper is on the design and performance analysis of practical distributed space-time codes for wireless relay networks with multiple antennas terminals. The amplify-andforward scheme is used in a way that each relay transmits a scaled version of the linear combination of the received symbols. We propose distributed generalized quasi-orthogonal space-time codes which are distributed among the source antennas and relays, and valid for any number of relays. Assuming M-PSK and M-QAM signals, we derive a formula for the symbol error probability of the investigated scheme over Rayleigh fading channels. For sufficiently large SNR, this paper derives closed-form average SER expression. The simplicity of the asymptotic results provides valuable insights into the performance of cooperative networks and suggests means of optimizing them. Our analytical results have been confirmed by simulation results, using full-rate full-diversity distributed codes.

Dynamically Reconfigurable Regular Expression Matching Architecture

Regular Expressions are generic representations for a string or a collection of strings. This paper focuses on implementation of a regular expression matching architecture on reconfigurable fabric like FPGA. We present a Nondeterministic Finite Automata based implementation with extended regular expression syntax set compared to previous approaches. We also describe a dynamically reconfigurable generic block that implements the supported regular expression syntax. This enables formation of the regular expression hardware by a simple cascade of generic blocks as well as a possibility for reconfiguring the generic blocks to change the regular expression being matched. Further,we have developed an HDL code generator to obtain the VHDL description of the hardware for any regular expression set. Our optimized regular expression engine achieves a throughput of 2.45 Gbps. Our dynamically reconfigurable regular expression engine achieves a throughput of 0.8 Gbps using 12 FPGA slices per generic block on Xilinx Virtex2Pro FPGA.

Integer Sequence window based Reconfigurable FIR filters

Conventional hardware implementation techniques for FIR filters require the computation of filter coefficients in software and have them stored in memory. This approach is static in the sense that any further fine tuning of the filter requires computation of new coefficients in software. In this paper, we propose an alternate technique for implementing FIR filters in hardware. We store a considerably large number of impulse response coefficients of the ideal filter (having box type frequency response) in memory. We then do the windowing process, on these coefficients, in hardware using integer sequences as window functions. The integer sequences are also generated in hardware. This approach offers the flexibility in fine tuning the filter, like varying the transition bandwidth around a particular cutoff frequency.