Backward switching phenomenon from field forced ferroelectric to antiferroelectric phases in antiferroelectric PbZrO3 thin films

Antiferroelectric materials (example: lead zirconate and modified lead zirconate stannate), in which a field-induced ferroelectric phase transition is feasible due to a small free energy difference between the ferroelectric and the antiferroelectric phases, are proven to be very good candidates for applications involving actuation and high charge storage devices. The property of reverse switching from the field-induced ferroelectric to antiferroelectric phases is studied as a function of temperature, applied electric field, and sample thickness in antiferroelectric lead zirconate thin films deposited by pulsed excimer laser ablation. The maximum released charge density was 22 μC/cm2 from a stored charge density of 36 μC/cm2 in a 0.55 μ thick lead zirconate thin film. This indicated that more than 60% of the stored charge could be released in less than 7 ns at room temperature for a field of 200 kV/cm. The content of net released charge was found to increase with increasing field strength, whereas with increasing temperature the released charge was found to decrease. Thickness-dependent studies on lead zirconate thin films showed that size effects relating to extrinsic and intrinsic pinning mechanisms controlled the released and induced charges through the intrinsic switching time. These results proved that antiferroelectric PZ thin films could be utilized in high-speed charge decoupling capacitors in microelectronics applications.

Design of a Low Power 64 Point FFT Architecture for WLAN Applications

This paper presents a Radix-4(3) based FFT architecture suitable for OFDM based WLAN applications. The radix-4(3) parallel unrolled architecture presented here, uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. A 64 point FFT processor based on the proposed architecture has been implemented in UMC 130nm 1P8M CMOS process with a maximum clock frequency of 100 MHz and area of 0.83mm(2). The proposed processor provides a throughput of four times the clock rate and can finish one 64 point FFT computation in 16 clock cycles. For IEEE 802.11a/g WLAN, the processor needs to be operated at a clock rate of 5 MHz with a power consumption of 2.27 mW which is 27% less than the previously reported low power implementations.

A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs

The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This paper presents a charge-pump (CP) mismatch current reduction technique utilizing an adaptive body bias tuning of CP transistors and a zero CP mismatch current tracking PLL architecture for reference spur suppression. A chip prototype of the proposed circuit was implemented in 0.13 mu m CMOS technology. The frequency synthesizer consumes 8.2 mA current from a 13 V supply voltage and achieves a phase noise of -96.01 dBc/Hz @ 1 MHz offset from a 2.4 GHz RF carrier. The charge-pump measurements using the proposed calibration technique exhibited a mismatch current of less than 0.3 mu A (0.55%) over the VCO control voltage range of 0.3-1.0 V. The closed loop measurements show a minimized static phase error of within +/- 70 ps and a similar or equal to 9 dB reduction in reference spur level across the PLL output frequency range 2.4-2.5 GHz. The presented CP calibration technique compensates for the DC current mismatch and the mismatch due to channel length modulation effect and therefore improves the performance of CP-PLLs in nano-meter CMOS implementations. (C) 2015 Elsevier Ltd. All rights reserved.

Integrating vertically aligned carbon nanotubes on micromechanical structures

The integration of high yield, uniform and preferential growth of vertically aligned carbon nanotubes (VACNT) on low stress micromechanical structures was analyzed. A combination of electron-beam crosslinked surface micromachining and direct current plasma enhanced chemical vapor deposition of electric field aligned carbon nanotubes was used for the analysis. The selective placement of high yield and uniform VACNTs on a partially suspended Ni/SiO2/Ti microstructure was also demonstrated.

Fabrication and electrical characteristics of carbon nanotube-based microcathodes for use in a parallel electron-beam lithography system

The development of the Nanolith parallel electron-beam writing head was discussed. The fabrication and electrical characteristics of carbon nanotube-based microcathodes for use in the lithographic system were described. The microcathode exhibited a peak current of 10.5 μA at 48 V when operated with a duty cycle of 0.5 percent.

Characteristics of multiwalled carbon nanotube nanobridges fabricated by poly(methylmethacrylate) suspended dispersion

Transport measurements were performed on individual PECVD grown MWCNT nanobridge structures. Temperature dependent conductance measurements show that as the temperature is decreased, the conductance also decreases. The nanotubes were able to carry high current densities with the observed maximum at ∼108 A/cm2. High volatile measurements reveal that the PECVD grown MWCNTs break down in segments of nanotube shells.

Fabrication of multiwalled carbon nanotube bridges by poly-methylmethacrylate suspended dispersion

Poly-methylmethacrylate suspended dispersion was used to fabricate multiwalled carbon nanotube (MWCNT) bridges. Using this technique, nanotubes could be suspended between metal electrodes without any chemical etching of the substrate. The electrical measurement on suspended MWCNT bridges shows that the room temperature resistance ranges from under a kω to a few Mω.

Tensile Tests Of Micro Anchors Anodically Bonded Between Pyrex Glass And Aluminum Thin Film Coated On Silicon Wafer

Micro anchor is a kind of typical structures in micro/nano electromechanical systems (MEMS/NEMS), and it can be made by anodic bonding process, with thin films of metal or alloy as an intermediate layer. At the relative low temperature and voltage, specimens with actually sized micro anchor structures were anodically bonded using Pyrex 7740 glass and patterned crystalline silicon chips coated with aluminum thin film with a thickness comprised between 50 nm and 230 nm. To evaluate the bonding quality, tensile pulling tests have been finished with newly designed flexible fixtures for these specimens. The experimental results exhibit that the bonding tensile strength increases with the bonding temperature and voltage, but it decreases with the increase of the thickness of Al intermediate layer. This kind of thickness effect of the intermediate layer was not mentioned in the literature on anodic bonding. (C) 2008 Elsevier Ltd. All rights reserved.