Comparative electrical behavior at low and high current of SnO(2)- and ZnO-based varistors

The complete I-V characteristics of SnO(2)-based varistors, particularly of the Pianaro system SCNCr consisting in 98.9%SnO(2)+1%CoO+0.05%Nb(2)O(5)+0.05%Cr(2)O(3), all in mol%, have been seldom reported in the literature. A comparative study at low and high currents of the nonohmic behavior of SCNCr- and ZnO-based varistors (modified Matsuoka system) is proposed in this work. The SCNCr system showed higher nonlinearity coefficients in the whole range of measured current. The electrical breakdown field (E(b)) was twice as high for the SCNCr system (5400 V/cm) than for the ZnO varistor (2600 V/cm) due to a smaller average grain size of the former (4.5 mu m) with respect to the latter (8.5 mu m). Nevertheless, we consider that another important factor responsible for the high E(b) in the SCNCr system is the great number of electrically active interfaces (85%) as determined with electrostatic force microscopy (EFM). It was also established that the SCNCr system might be produced in disks of smaller dimensions than that of commercial ZnO-based product, with a 5.0 cm(-1) minimal area-volume (A/V) ratio. The SCNCr reached the saturation current in a short time because of the high resistivity of the grains, which is five times higher than that of the grains in ZnO-based varistors.

Low-voltage varistor based on (Sn,Ti)O-2 ceramics

A description is given of the nonohmic behavior obtained in (SnxTi1-x)O-2-based systems. A matrix founded on (SnxTi1-x)O-2-based systems doped with Nb2O5 leads to a low-voltage varistor system with nonlinear coefficient values of similar to9. The presence of the back-to-back Schottky-type barrier is observed based on the voltage dependence of the capacitance. When doped with CoO, the (SnxTi1-x)O(2)(.)based system presents higher nonlinear coefficient values (>30) than does the SnO2-based varistor system.

PROCESSING AND CHARACTERIZATION OF LOW-VOLTAGE VARISTORS

ZnO seed particles and Cr2O3 were used in this study to control the microstructure of ZnO varistors. The seed particles were prepared by adding 1.0 mol % BaO to ZnO. The powder was then calcined at 800-degrees-C for 2 h, pressed into pellets and sintered at 1400-degrees-C for 8 h. The sintered ZnO was ground and the BaO eliminated by washing in water. The remaining ZnO powder was classified into a size fraction ranging from 38 to 149 mum. The addition of a small amount (1 weight %) ZnO seed grains produces varistors with low breakdown voltages (7.6 V/mm) and an alpha coefficient of approximately 10. The addition of Cr2O3 stabilizes the spinel phase yielding a more homogeneous microstructure, but degraded electrical behaviour of the ZnO varistor.

A CMOS/SOI single-input PWM discriminator for low-voltage body-implanted applications

A CMOS/SOI circuit to decode Pulse-Width Modulation (PWM) signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a novel double-integration concept and does not require low-pass filtering. Non-overlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 mum single-metal thin-film CMOS/SOI fabrication process and has an effective area of 2 mm(2). Measured resolution of encoding parameter a is better than 10% at 6 MHz and V-DD = 3.3 V. Idle-mode consumption is 340 LW. Pulses of frequencies up to 15 MHz and alpha = 10% can be discriminated for 2.3 V less than or equal to V-DD less than or equal to 3.3 V. Such an excellent immunity to V-DD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.

A linearly tunable low-voltage CMOS transconductor with improved common-mode stability and its application to (gm)-C filters

A linearly tunable low-voltage CMOS transconductor featuring a new adaptative-bias mechanism that considerably improves the stability of the processed-signal common,mode voltage over the tuning range, critical for very-low voltage applications, is introduced. It embeds a feedback loop that holds input devices on triode region while boosting the output resistance. Analysis of the integrator frequency response gives an insight into the location of secondary poles and zeros as function of design parameters. A third-order low-pass Cauer filter employing the proposed transconductor was designed and integrated on a 0.8-mum n-well CMOS standard process. For a 1.8-V supply, filter characterization revealed f(p) = 0.93 MHz, f(s) = 1.82 MHz, A(min) = 44.08, dB, and A(max) = 0.64 dB at nominal tuning. Mined by a de voltage V-TUNE, the filter bandwidth was linearly adjusted at a rate of 11.48 kHz/mV over nearly one frequency decade. A maximum 13-mV deviation on the common-mode voltage at the filter output was measured over the interval 25 mV less than or equal to V-TUNE less than or equal to 200 mV. For V-out = 300 mV(pp) and V-TUNE = 100 mV, THD was -55.4 dB. Noise spectral density was 0.84 muV/Hz(1/2) @1 kHz and S/N = 41 dB @ V-out = 300 mV(pp) and 1-MHz bandwidth. Idle power consumption was 1.73 mW @V-TUNE = 100 mV. A tradeoff between dynamic range, bandwidth, power consumption, and chip area has then been achieved.

On designing linearly-tunable ultra-low voltage CMOS gm-C filters

A linearly-tunable ULV transconductor featuring excellent stability of the processed signal common-mode voltage upon tuning, critical for very-low voltage applications, is presented. Its employment to the synthesis of CMOS gm-C high-frequency and voiceband filters is discussed. SPICE data describe the filter characteristics. For a 1.3 V-supply, their nominal passband frequencies are 1.0 MHz and 3.78 KHz, respectively, with tuning rates of 12.52 KHz/mV and 0.16 KHz/m V, input-referred noise spectral density of 1.3 μV/Hz1/2 and 5.0μV/Hz1/2 and standby consumption of 0.87 mW and 11.8 μW. Large-signal distortion given by THD = 1% corresponds to a differential output-swing of 360 mVpp and 480 mVpp, respectively. Common-mode voltage deviation is less than 4 mV over tuning interval.

An accurate low-voltage analog memory-cell with built-in multiplication

A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gain-boosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transconductor and the stored voltage is provided. Designing complies with a low-voltage 1.2μm N-well CMOS fabrication process. For a 1.3V-supply, CCELL=3.6pF and sampling interval is 0.25μA≤ ISAMPLE ≤ 0.75μA. The specified retention time is 1.28ms and corresponds to a charge-variation of 1% due to junction leakage @75°C. A range of MR simulations confirm circuit performance. Absolute read-out error is below O.40% while the four-quadrant multiplier nonlinearity, at full-scale is 8.2%. Maximum stand-by consumption is 3.6μW/cell.

A low-voltage programmable-gain CMOS amplifier with very-low temperature-drift

A new topology for a LVLP variable-gain CMOS amplifier is presented. Input- and load-stage are built around triode-transconductors so that voltage-gain is fully defined by a linear relationship involving only device-geometries and biases. Excellent gain-accuracy, temperature-insensitivity; and wide range of programmability, are thus achieved. Moreover, adaptative biasing improves the common-mode voltage stability upon gain-adjusting. As an example, a 0-40dB programmablegain audio-amplifier is designed. Its performance is supported by a range of simulations. For VDD=1.8V and 20dB-nominal gain, one has Av=19.97dB, f3db=770KHz and quiescent dissipation of 378μW. Over temperatures from -25°C to 125°C, the 0. ldB-bandwidth is 52KHz. Dynamic-range is optimized to 57.2dB and 42.6dB for gains of 20dB and 40dB, respectively. THD figures correspond to -60.6dB@Vout= 1Vpp and -79.7dB@Vout= 0.5 Vpp. A nearly constant bandwidth for different gains is also attained.

A linearly-tunable OTA-C sinusoidal oscillator for low-voltage applications

A low-voltage, low-power OTA-C sinusoidal oscillator based on a triode-MOSFET transconductor is here discussed. The classical quadrature model is employed and the transconductor inherent nonlinear characteristic with input voltage is used as the amplitude-stabilization element. An external bias VTUNE linearly adjusts the oscillation frequency. According to a standard 0.8μm CMOS n-well process, a prototype was integrated, with an effective area of 0.28mm2. Experimental data validate the theoretical analysis. For a single 1.8V-supply and 100mV≤VTUNE≤250mV, the oscillation frequency fo ranges from 0.50MHz to 1.125MHz, with a nearly constant gain KVCO=4.16KHz/mV. Maximum output amplitude is 374mVpp @1.12MHz. THD is -41dB @321mVpp. Maximum average consumption is 355μW.

A low-voltage low-sensitivity sinusoidal VCO for DPLL realizations

A quasi-sinusoidal linearly tunable OTA-C VCO built with triode-region transconductors is presented. Oscillation upon power-on is ensured by RHP poles associated with gate-drain capacitances of OTA input devices. Since the OTA nonlinearity stabilizes the amplitude, the oscillation frequency f0 is first-order independent of VDD, making the VCO adequate to mixed-mode designs. A range of simulations attests the theoretical analysis. As part of a DPLL, the VCO was prototyped on a 0.8μm CMOS process, occupying an area of 0.15mm2. Nominal f0 is 1MHz, with K VCo=8.4KHz/mV. Measured sensitivity to VDD is below 2.17, while phase noise is -86dBc at 100-KHz offset. The feasibility of the VCO for higher frequencies is verified by a redesign based on a 0.35μm CMOS process and VDD=3.3V, with a linear frequency-span of l3.2MHz - 61.5MHz.

Efficiency analysis of an isolated high voltage gain converter operating in resonant and non-resonant mode

This paper presents an efficiency investigation of an isolated high step-up ratio dc-dc converter aimed to be used for energy processing from low-voltage high-current energy sources, like batteries, photovoltaic modules or fuel-cells. The considered converter consists of an interleaved active clamp flyback topology combined with a voltage multiplier at the transformer secondary side capable of two different operating modes, i.e. resonant and non-resonant according to the design of the output capacitors. The main goal of this paper is to compare these two operating modes from the component losses point of view with the aim of maximize the overall converter efficiency. The approach is based on losses prediction using steady-state theoretical models (designed in Mathcad environment), taking into account both conduction and switching losses. The models are compared with steady-state simulations and experimental results considering different operating modes to validate the approach. © 2012 IEEE.

Comparative electrical behavior at low and high current of SnO(2)- and ZnO-based varistors

The complete I-V characteristics of SnO(2)-based varistors, particularly of the Pianaro system SCNCr consisting in 98.9%SnO(2)+1%CoO+0.05%Nb(2)O(5)+0.05%Cr(2)O(3), all in mol%, have been seldom reported in the literature. A comparative study at low and high currents of the nonohmic behavior of SCNCr- and ZnO-based varistors (modified Matsuoka system) is proposed in this work. The SCNCr system showed higher nonlinearity coefficients in the whole range of measured current. The electrical breakdown field (E(b)) was twice as high for the SCNCr system (5400 V/cm) than for the ZnO varistor (2600 V/cm) due to a smaller average grain size of the former (4.5 mu m) with respect to the latter (8.5 mu m). Nevertheless, we consider that another important factor responsible for the high E(b) in the SCNCr system is the great number of electrically active interfaces (85%) as determined with electrostatic force microscopy (EFM). It was also established that the SCNCr system might be produced in disks of smaller dimensions than that of commercial ZnO-based product, with a 5.0 cm(-1) minimal area-volume (A/V) ratio. The SCNCr reached the saturation current in a short time because of the high resistivity of the grains, which is five times higher than that of the grains in ZnO-based varistors.

Improved low-voltage-ride-through capability of fixed-speed wind turbines using decentralised control of STATCOM with energy storage system

The design and implementation of a new control scheme for reactive power compensation, voltage regulation and transient stability enhancement for wind turbines equipped with fixed-speed induction generators (IGs) in large interconnected power systems is presented in this study. The low-voltage-ride-through (LVRT) capability is provided by extending the range of the operation of the controlled system to include typical post-fault conditions. A systematic procedure is proposed to design decentralised multi-variable controllers for large interconnected power systems using the linear quadratic (LQ) output-feedback control design method and the controller design procedure is formulated as an optimisation problem involving rank-constrained linear matrix inequality (LMI). In this study, it is shown that a static synchronous compensator (STATCOM) with energy storage system (ESS), controlled via robust control technique, is an effective device for improving the LVRT capability of fixed-speed wind turbines.

HIGH VOLTAGE PULSED CURRENT STIMULATION OF THE SCIATIC NERVE IN RATS: ANALYSIS BY THE SFI

Objective: To analyze the efficiency of high voltage pulsed current (HVPC) with early application in three different sites, in the regeneration of the sciatic nerve in rats submitted to crush injury, the sciatic functional index (SFI) was used to assess the functional recovery. Methods: After crushing of the nerve, 57 animals were submitted to cathodal HVPC at frequency of 50Hz and voltage of 100V, 20 minutes per day, 5 days per week. The rats were divided into five groups: control group; ganglion group; ganglion + muscle group; muscle group; and sham group. The SFI was determined weekly for seven weeks, from the preoperative period to the 6th postoperative week. Results: Compared with the control group, the results showed a significantly better performance of group 2 for the first 3 weeks; group 3 showed significantly better performance in the third week; and group 4 showed a significantly negative performance during the 481 and 6th weeks. Conclusion: Early application of HVPC had a positive effect in the treatment of the spinal cord region and the sciatic nerve root ganglion with a dispersive electrode on the contralateral lumbar region or on the gastrocnemius. However, HVPC had a negative effect in the treatment with an active electrode on the gastrocnemius and a dispersive electrode on the contralateral thigh. Level of evidence II, Prospective comparative study.