Modelo matemático de linhas de transmissão, contemplando influências ambientais, para o trecho Guamá-Utinga, localizado em Belém, pertencente à Eletronorte

Teoricamente, a predição de falha em cadeia de isoladores pode ser observada pela verificação do comportamento harmônico da corrente através dos isoladores, chamada de corrente de fuga. Isto porque a capacitância de uma cadeia de isoladores permite a passagem das componentes harmônicas de maior ordem da corrente na linha. No entanto os projetos e planejamento de linhas de transmissão só levam em consideração as dimensões e geometrias da linha; esquecendo ou ignorando os efeitos ambientais em uma linha de transmissão. A omissão de tais efeitos, podem confundir um diagnóstico de falha no sistema de isolação da linha, de forma que foi necessário desenvolver uma metodologia para determinação dos valores dos parâmetros elétricos, resistência elétrica e capacitância em função de variáveis ambientais como: temperatura ambiente, radiação solar, umidade relativa do ar, velocidade do vento e direção do vento, particularmente a determinação do comportamento da capacitância, em função dessas variáveis ambientais se deu de maneira inovadora e experimental, tendo em vista obter um modelo matemático de linha de transmissão mais realista e dinâmico, que possa identificar de maneira precisa os parâmetros elétricos, sob a influência das variáveis ambientais. Nesse trabalho é desenvolvido esse modelo, que, além de ser alimentado com dados elétricos e ambientais reais, é feito o estudo da decomposição harmônica da corrente de fuga; além da comparação com resultados de outros modelos já existentes. São realizadas ainda, simulações de falhas virtuais, que compravam a eficiência e limitações do modelo, além de sugerir uma forma de monitoração em tempo real e a baixos custos.

Síntese e caracterização elétrica de filmes varistores à base de 'SN''O IND.2' modificados superficialmente por difusão 'CR POT.3+' na região do contorno de grão

Pós-graduação em Química - IQ

Electrical behavior of Bi0.95Nd0.05FeO3 thin films grown by the soft chemical method

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Influence of the concentration of Sb2O3 on the electrical properties of SnO2 varistors

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Piezoresponse force microscopy behaviour of Bi4Ti3O12 ceramics with various excess bismuth

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Electrical Properties at Grain Boundaries Influenced by Cr3+ Diffusion in SnO2.ZnO.Nb2O5-Films Varistor Prepared by Electrophoresis Deposition

SnO2-based varistors are strong candidates to replace the ZnO-based varistors due to ordering fewer additives to improve its electrical behavior as well as by showing similar nonlinear characteristics of ZnO varistors. In this work, SnO2-nanoparticles based-varistors with addition of 1.0 %mol of ZnO and 0.05 %mol of Nb2O5 were synthesized by chemical route. SnO2.ZnO.Nb2O5-films with 5 μm of thickness were obtained by electrophoretic deposition (EPD) of the nanoparticles on Si/Pt substrate from alcoholic suspension of SnO2-based powder. The sintering step was carried out in a microwave oven at 1000 °C for 40 minutes. Then, Cr3+ ions were deposited on the films surface by EPD after the sintering step. Each sample was submitted to different thermal treatments to improve the varistor behavior by diffusion of ions in the samples. The films showed a nonlinear coefficient (α) greater than 9, breakdown voltage (VR) around 60 V, low leakage current (IF ≈ 10-6 A), height potential barrier above 0.5 eV and grain boundary resistivity upward of 107 Ω.cm.

Electrophoretic deposition of (Zn, Nb)SnO2-films varistor superficially modified with Cr3+

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Fabrication and structural characterization of bismuth niobate thin films grown by chemical solution deposition

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Heterojunction between Al2O3 and SnO2 thin films for application in transparent FET

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Ferroelectric and dielectric characteristics of Bi3.25La0.75Ti3O12 thin films prepared by the polymeric precursor method

The ferroelectric properties and leakage current mechanisms of preferred oriented Bi3.25La0.75 Ti3O12 (BLT) thin films deposited on La0.5Sr0.5CoO3 (LSCO) by the polymeric precursor method were investigated. Atomic force microscopy indicates that the deposited films exhibit a dense microstructure with a rather smooth surface morphology. The improved ferroelectric and leakage current characteristics can be ascribed to the plate-like grains of the BLT films. © 2006 Trans Tech Publications, Switzerland.

Análise da resposta dielétrica e varistora de compostos cerâmicos multifásicos à base de Ca2CU2Ti4-xSnxO12 (0,0 < x< 4,0)

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Performance of electronic devices submitted to X-rays and high energy proton beams

In this work we have studied the radiation effects on MOSFET electronic devices. The integrated circuits were exposed to 10 key X-ray radiation and 2.6 MeV energy proton beam. We have irradiated MOSFET devices with two different geometries: rectangular-gate transistor and circular-gate transistor. We have observed the cumulative dose provokes shifts on the threshold voltage and increases or decreases the transistor's off-state and leakage current. The position of the trapped charges in modern CMOS technology devices depends on radiation type, dose rate, total dose, applied bias and is a function of device geometry. We concluded the circular-gate transistor is more tolerant to radiation than the rectangular-gate transistor. (C) 2011 Elsevier B.V. All rights reserved.

Detection of partial discharges at field in SF6 insulated equipments

This paper presents the results of research aiming to develop partial discharge detection techniques in high voltage equipment, at substation environment. Measurements of high frequency components of leakage current, at equipments' grounding conductor, were performed. This procedure was performed with the equipment energized and without disconnecting it from the system. The partial discharge generated current pulse is picked up by a high frequency CT, and is detected by an oscilloscope. The partial discharge identification was made considering previously obtained laboratory results, where partial discharges were characterized by means of its time domain signatures. This paper focuses measurements in SF6 circuit breakers. Encouraging results were obtained, showing the feasibility of detecting partial discharges in energized equipment in the laboratory and in the field, in a substation environment, using this method.

Tecniche di progettazione tollerante alle variazioni per circuiti digitali in tecnologie nanometriche

The digital electronic market development is founded on the continuous reduction of the transistors size, to reduce area, power, cost and increase the computational performance of integrated circuits. This trend, known as technology scaling, is approaching the nanometer size. The lithographic process in the manufacturing stage is increasing its uncertainty with the scaling down of the transistors size, resulting in a larger parameter variation in future technology generations. Furthermore, the exponential relationship between the leakage current and the threshold voltage, is limiting the threshold and supply voltages scaling, increasing the power density and creating local thermal issues, such as hot spots, thermal runaway and thermal cycles. In addiction, the introduction of new materials and the smaller devices dimension are reducing transistors robustness, that combined with high temperature and frequently thermal cycles, are speeding up wear out processes. Those effects are no longer addressable only at the process level. Consequently the deep sub-micron devices will require solutions which will imply several design levels, as system and logic, and new approaches called Design For Manufacturability (DFM) and Design For Reliability. The purpose of the above approaches is to bring in the early design stages the awareness of the device reliability and manufacturability, in order to introduce logic and system able to cope with the yield and reliability loss. The ITRS roadmap suggests the following research steps to integrate the design for manufacturability and reliability in the standard CAD automated design flow: i) The implementation of new analysis algorithms able to predict the system thermal behavior with the impact to the power and speed performances. ii) High level wear out models able to predict the mean time to failure of the system (MTTF). iii) Statistical performance analysis able to predict the impact of the process variation, both random and systematic. The new analysis tools have to be developed beside new logic and system strategies to cope with the future challenges, as for instance: i) Thermal management strategy that increase the reliability and life time of the devices acting to some tunable parameter,such as supply voltage or body bias. ii) Error detection logic able to interact with compensation techniques as Adaptive Supply Voltage ASV, Adaptive Body Bias ABB and error recovering, in order to increase yield and reliability. iii) architectures that are fundamentally resistant to variability, including locally asynchronous designs, redundancy, and error correcting signal encodings (ECC). The literature already features works addressing the prediction of the MTTF, papers focusing on thermal management in the general purpose chip, and publications on statistical performance analysis. In my Phd research activity, I investigated the need for thermal management in future embedded low-power Network On Chip (NoC) devices.I developed a thermal analysis library, that has been integrated in a NoC cycle accurate simulator and in a FPGA based NoC simulator. The results have shown that an accurate layout distribution can avoid the onset of hot-spot in a NoC chip. Furthermore the application of thermal management can reduce temperature and number of thermal cycles, increasing the systemreliability. Therefore the thesis advocates the need to integrate a thermal analysis in the first design stages for embedded NoC design. Later on, I focused my research in the development of statistical process variation analysis tool that is able to address both random and systematic variations. The tool was used to analyze the impact of self-timed asynchronous logic stages in an embedded microprocessor. As results we confirmed the capability of self-timed logic to increase the manufacturability and reliability. Furthermore we used the tool to investigate the suitability of low-swing techniques in the NoC system communication under process variations. In this case We discovered the superior robustness to systematic process variation of low-swing links, which shows a good response to compensation technique as ASV and ABB. Hence low-swing is a good alternative to the standard CMOS communication for power, speed, reliability and manufacturability. In summary my work proves the advantage of integrating a statistical process variation analysis tool in the first stages of the design flow.

In situ real-time investigation of Organic Ultra-Thin-Film transistors: growth, electrical properties and biosensing applications

Organic electronics has grown enormously during the last decades driven by the encouraging results and the potentiality of these materials for allowing innovative applications, such as flexible-large-area displays, low-cost printable circuits, plastic solar cells and lab-on-a-chip devices. Moreover, their possible field of applications reaches from medicine, biotechnology, process control and environmental monitoring to defense and security requirements. However, a large number of questions regarding the mechanism of device operation remain unanswered. Along the most significant is the charge carrier transport in organic semiconductors, which is not yet well understood. Other example is the correlation between the morphology and the electrical response. Even if it is recognized that growth mode plays a crucial role into the performance of devices, it has not been exhaustively investigated. The main goal of this thesis was the finding of a correlation between growth modes, electrical properties and morphology in organic thin-film transistors (OTFTs). In order to study the thickness dependence of electrical performance in organic ultra-thin-film transistors, we have designed and developed a home-built experimental setup for performing real-time electrical monitoring and post-growth in situ electrical characterization techniques. We have grown pentacene TFTs under high vacuum conditions, varying systematically the deposition rate at a fixed room temperature. The drain source current IDS and the gate source current IGS were monitored in real-time; while a complete post-growth in situ electrical characterization was carried out. At the end, an ex situ morphological investigation was performed by using the atomic force microscope (AFM). In this work, we present the correlation for pentacene TFTs between growth conditions, Debye length and morphology (through the correlation length parameter). We have demonstrated that there is a layered charge carriers distribution, which is strongly dependent of the growth mode (i.e. rate deposition for a fixed temperature), leading to a variation of the conduction channel from 2 to 7 monolayers (MLs). We conciliate earlier reported results that were apparently contradictory. Our results made evident the necessity of reconsidering the concept of Debye length in a layered low-dimensional device. Additionally, we introduce by the first time a breakthrough technique. This technique makes evident the percolation of the first MLs on pentacene TFTs by monitoring the IGS in real-time, correlating morphological phenomena with the device electrical response. The present thesis is organized in the following five chapters. Chapter 1 makes an introduction to the organic electronics, illustrating the operation principle of TFTs. Chapter 2 presents the organic growth from theoretical and experimental points of view. The second part of this chapter presents the electrical characterization of OTFTs and the typical performance of pentacene devices is shown. In addition, we introduce a correcting technique for the reconstruction of measurements hampered by leakage current. In chapter 3, we describe in details the design and operation of our innovative home-built experimental setup for performing real-time and in situ electrical measurements. Some preliminary results and the breakthrough technique for correlating morphological and electrical changes are presented. Chapter 4 meets the most important results obtained in real-time and in situ conditions, which correlate growth conditions, electrical properties and morphology of pentacene TFTs. In chapter 5 we describe applicative experiments where the electrical performance of pentacene TFTs has been investigated in ambient conditions, in contact to water or aqueous solutions and, finally, in the detection of DNA concentration as label-free sensor, within the biosensing framework.