Digital Dead Time Logic and Protection Circuitry for PWM Voltage Source Converters

Power semiconductor devices have finite turn on and turn off delays that may not be perfectly matched. In a leg of a voltage source converter, the simultaneous turn on of one device and the turn off of the complementary device will cause a DC bus shoot through, if the turn off delay is larger than the turn on delay time. To avoid this situation it is common practice to blank the two complementary devices in a leg for a small duration of time while switching, which is called dead time. This paper proposes a logic circuit for digital implementation required to control the complementary devices of a leg independently and at the same time preventing cross conduction of devices in a leg, and while providing accurate and stable dead time. This implementation is based on the concept of finite state machines. This circuit can also block improper PWM pulses to semiconductor switches and filters small pulses notches below a threshold time width as the narrow pulses do not provide any significant contribution to average pole voltage, but leads to increased switching loss. This proposed dead time logic has been implemented in a CPLD and is implemented in a protection and delay card for 3- power converters.

Gate Drive Card for High Power Three Phase PWM Converters

Gate driver is an integral part of every power converter, drives the power semiconductor devices and also provides protection for the switches against short-circuit events and over-voltages during shut down. Gate drive card for IGBTs and MOSFETs with basic features can be designed easily by making use of discrete electronic components. Gate driver ICs provides attractive features in a single package, which improves reliability and reduces effort of design engineers. Either case needs one or more isolated power supplies to drive each power semiconductor devices and provide isolation to the control circuitry from the power circuit. The primary emphasis is then to provide simplified and compact isolated power supplies to the gate drive card with the requisite isolation strength and which consumes less space, and for providing thermal protection to the power semiconductor modules for 3-� 3 wire or 4 wire inverters.

Modulation Diversity for Spatial Modulation Using Complex Interleaved Orthogonal Design

In this paper, we propose modulation diversity techniques for Spatial Modulation (SM) system using Complex Interleaved Orthogonal Design (CIOD). Specifically, we show that the standard SM scheme can achieve a transmit diversity order of two by using the CIOD meant for two transmit antenna system without incurring any additional system complexity or bandwidth requirement. Furthermore, we propose a low-complexity maximum likelihood detector for our CIOD based SM schemes by exploiting the structure of the CIOD. We show with our simulation results that the proposed schemes offer transmit diversity order of two and give a better symbol error rate performance than the conventional SM scheme.

Interleaved winding and suppression of natural frequencies

Ideally, it is desirable to design and manufacture a transformer winding that can render all its internal resonances non-excitable. This study examines the effectiveness of an interleaved winding in achieving this goal. While investigating its effectiveness, it led to the establishment of a much desired theoretical basis that reinforces the reasons put forward in the literature to explain internal insulation failures observed in interleaved windings used in extra high voltage (EHV) transformers. Numerical calculations along with experimental verification on actual transformer windings are presented. This study reveals that most of the natural frequencies that are normally non-excitable in the line and neutral current responses of an interleaved winding have been rendered excitable in the disk-to-disk voltages, thus, providing favourable conditions for insulation overstress because of resonant overvoltages. Prevalence of such a condition is an inherent characteristic of interleaved windings.

Apparatus and method for heat-run test on high-power PWM converters with low energy expenditure

Before installation, a voltage source converter is usually subjected to heat-run test to verify its thermal design and performance under load. For heat-run test, the converter needs to be operated at rated voltage and rated current for a substantial length of time. Hence, such tests consume huge amount of energy in case of high-power converters. Also, the capacities of the source and loads available in the research and development (R&D) centre or the production facility could be inadequate to conduct such tests. This paper proposes a method to conduct heat-run tests on high-power, pulse width modulated (PWM) converters with low energy consumption. The experimental set-up consists of the converter under test and another converter (of similar or higher rating), both connected in parallel on the ac side and open on the dc side. Vector-control or synchronous reference frame control is employed to control the converters such that one draws certain amount of reactive power and the other supplies the same; only the system losses are drawn from the mains. The performance of the controller is validated through simulation and experiments. Experimental results, pertaining to heat-run tests on a high-power PWM converter, are presented at power levels of 25 kVA to 150 kVA.

Common-Mode Injection PWM for Parallel Converters

The ac-side terminal voltages of parallel-connected converters are different if the line reactive drops of the individual converters are different. This could result either from differences in per-phase inductances or from differences in the line currents of the converters. In such cases, the modulating signals are different for the converters. Hence, the common-mode (CM) voltages for the converters, injected by conventional space vector pulsewidth modulation (CSVPWM) to increase dc-bus utilization, are different. Consequently, significant low-frequency zero-sequence circulating currents result. This paper proposes a new modulation method for parallel-connected converters with unequal terminal voltages. This method does not cause low-frequency zero-sequence circulating currents and is comparable with CSVPWM in terms of dc-bus utilization and device power loss. Experimental results are presented at a power level of 150 kVA from a circulating-power test setup, where the differences in converter terminal voltages are quite significant.

Computationally efficient models for simulation of non-ideal DC-DC converters operating in continuous and discontinuous conduction modes

This paper discusses dynamic modeling of non-isolated DC-DC converters (buck, boost and buck-boost) under continuous and discontinuous modes of operation. Three types of models are presented for each converter, namely, switching model, average model and harmonic model. These models include significant non-idealities of the converters. The switching model gives the instantaneous currents and voltages of the converter. The average model provides the ripple-free currents and voltages, averaged over a switching cycle. The harmonic model gives the peak to peak values of ripple in currents and voltages. The validity of all these models is established by comparing the simulation results with the experimental results from laboratory prototypes, at different steady state and transient conditions. Simulation based on a combination of average and harmonic models is shown to provide all relevant information as obtained from the switching model, while consuming less computation time than the latter.

NUMERICAL ANALYSIS OF THE FLOWFIELD IN A SUPERSONIC COIL WITH AN INTERLEAVED JET CONFIGURATION AND ITS EFFECT ON THE GAIN DISTRIBUTION

In a supersonic chemical oxygen-iodine laser (COIL) operating without primary buffer gas, the features of flowfield have significant effects on the Laser efficiency and beam quality. In this paper three-dimensional, multi-species, chemically reactive CFD technology was used to study the flowfield in mixing nozzle implemented with a supersonic interleaving jet configuration. The features of the flowfield as well as its effect on the spatial distribution of small signal gain were analyzed.