The 1998 Faial earthquake, Azores: Evidence for a transform fault associated with the Nubia-Eurasia plate boundary?

With very few exceptions, M > 4 tectonic earthquakes in the Azores show normal fault solution and occur away from the islands. Exceptionally, the 1998 shock was pure strike-slip and occurred within the northern edge of the Pico-Faial Ridge. Fault plane solutions show two possible planes of rupture striking ENE-WSW (dextral) and NNW-SSE (sinistral). The former has not been recognised in the Azores, but is parallel to the transform direction related to the relative motion between the Eurasia and Nubia plates. Therefore, the main question we address in the present study is: do transform faults related to the Eurasia/Nubia plate boundary exist in the Azores? Knowing that the main source of strain is related to plate kinematics, we conclude that the sinistral strike-slip NNW-SSE fault plane solution is not consistent with either the fault dip (ca. 65, which is typical of a normal fault) or the ca. ENE-WSW direction of maximum extension; both are consistent with a normal fault, as observed in most major earthquakes on faults striking around NNW-SSE in the Azores. In contrast, the dextral strike-slip ENE-WSW fault plane solution is consistent with the transform direction related to the anticlockwise rotation of Nubia relative to Eurasia. Altogether, tectonic data, measured ground motion, observed destruction, and modelling are consistent with a dextral strike-slip source fault striking ENE-WSW. Furthermore, the bulk clockwise rotation measured by GPS is typical of bookshelf block rotations observed at the termination of such master strike-slip faults. Therefore, we suggest that the 1998 earthquake can be related to the WSW termination of a transform (ENE-WSW fault plane solution) associated with the Nubia-Eurasia diffuse plate boundary. (C) 2014 Elsevier B.V. All rights reserved.

Real time fault injection using a modified debugging infrastructure

Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements

Real time fault injection using enhanced OCD -- a performance analysis

Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanisms present in modern electronic devices. The main objective is the injection of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented and compared in terms of performance gain and logic overhead.

Using NEXUS compliant debuggers for real time fault injection on microprocessors

As electronic devices get smaller and more complex, dependability assurance is becoming fundamental for many mission critical computer based systems. This paper presents a case study on the possibility of using the on-chip debug infrastructures present in most current microprocessors to execute real time fault injection campaigns. The proposed methodology is based on a debugger customized for fault injection and designed for maximum flexibility, and consists of injecting bit-flip type faults on memory elements without modifying or halting the target application. The debugger design is easily portable and applicable to different architectures, providing a flexible and efficient mechanism for verifying and validating fault tolerant components.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

A framework for fault tolerant real time systems based on reconfigurable FPGAs

To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

The Prognostic Impact of Renal Failure in Patients with ST-Segment Elevation Acute Myocardial Infarction

INTRODUCTION: Renal insufficiency (RI) is associated with higher morbidity and mortality in patients (P) with coronary artery disease and in P submitted to angioplasty. In ST-segment elevation acute myocardial infarction (STEAMI), this impact has not been well demonstrated. AIM: To evaluate the impact of RI in P with STEAMI. METHODS: We evaluated 160 P admitted with STEAMI, mean age of 62+/-14 years, 76% male. We determined creatinine levels on admission. RI was defined as a level >1.5 mg/dl. Analysis of clinical, electrocardiographic and laboratory variables was performed, in relation to the endpoint defined as the occurrence of death at 30-day follow-up. RESULTS: There were 16 deaths (10%) at 30-day follow-up. P with RI (n=21) were older (68+/-11 vs 61+/-14 years, p<0.001), more often had diabetes (57 vs 24 %, p=0.004) and presented more often with Killip class > or =2 (57 vs 12%, p<0.001). The use of statins (62 vs 83%, p=0.05) and beta-blockers (24 vs 65%, p<0.001) was lower in P with RI. Mortality was higher in RI P (62 vs 2%, p<0.001). The univariate predictors of death were age > or =75 years, diabetes, Killip class > or =2 on admission, RI, non-use of statins and beta-blockers and use of diuretics. In multivariate analysis, independent predictors of death at 30 days were RI (HR 29.6, 95% CI 6.3-139.9, p<0.001) and non-use of beta-blockers (HR 0.13, 95% CI 0.02-1.01, p=0.01). CONCLUSION: In P admitted for STEAMI, the presence of RI was an independent predictor of death at 30 days whereas the usage of beta-blockers was protective.

Passive Fault-Tolerance Management in Component-based Embedded Systems

It is imperative to accept that failures can and will occur, even in meticulously designed distributed systems, and design proper measures to counter those failures. Passive replication minimises resource consumption by only activating redundant replicas in case of failures, as typically providing and applying state updates is less resource demanding than requesting execution. However, most existing solutions for passive fault tolerance are usually designed and configured at design time, explicitly and statically identifying the most critical components and their number of replicas, lacking the needed flexibility to handle the runtime dynamics of distributed component-based embedded systems. This paper proposes a cost-effective adaptive fault tolerance solution with a significant lower overhead compared to a strict active redundancy-based approach, achieving a high error coverage with the minimum amount of redundancy. The activation of passive replicas is coordinated through a feedback-based coordination model that reduces the complexity of the needed interactions among components until a new collective global service solution is determined, improving the overall maintainability and robustness of the system.

Is It Possible to Simplify Risk Stratification Scores for Patients with ST-Segment Elevation Myocardial Infarction Undergoing Primary Angioplasty?

INTRODUCTION: There are several risk scores for stratification of patients with ST-segment elevation myocardial infarction (STEMI), the most widely used of which are the TIMI and GRACE scores. However, these are complex and require several variables. The aim of this study was to obtain a reduced model with fewer variables and similar predictive and discriminative ability. METHODS: We studied 607 patients (age 62 years, SD=13; 76% male) who were admitted with STEMI and underwent successful primary angioplasty. Our endpoints were all-cause in-hospital and 30-day mortality. Considering all variables from the TIMI and GRACE risk scores, multivariate logistic regression models were fitted to the data to identify the variables that best predicted death. RESULTS: Compared to the TIMI score, the GRACE score had better predictive and discriminative performance for in-hospital mortality, with similar results for 30-day mortality. After data modeling, the variables with highest predictive ability were age, serum creatinine, heart failure and the occurrence of cardiac arrest. The new predictive model was compared with the GRACE risk score, after internal validation using 10-fold cross validation. A similar discriminative performance was obtained and some improvement was achieved in estimates of probabilities of death (increased for patients who died and decreased for those who did not). CONCLUSION: It is possible to simplify risk stratification scores for STEMI and primary angioplasty using only four variables (age, serum creatinine, heart failure and cardiac arrest). This simplified model maintained a good predictive and discriminative performance for short-term mortality.

Multiple Mechanical Complications in ST-Segment Elevation Myocardial Infarction with Angiographically Normal Coronary Arteries

This case report discusses an unusual presentation of ST-segment elevation myocardial infarction (STEMI) with normal coronary arteries and severe mechanical complications successfully treated with surgery. An 82-year-old man presented STEMI with angiographically normal coronary arteries and no major echocardiographic alterations at discharge. At the first month follow-up, he complained of fatigue and dyspnea, and contrast echocardiography complemented by cardiac magnetic resonance imaging revealed a large left ventricular apical aneurysm with a thrombus communicating by two jets of a turbulent flow to an aneurysmatic formation of the right ventricular apex. The patient underwent a Dor procedure, which was successful. Ventricular septal defects and ventricular aneurysms are rare but devastating complications of STEMI, with almost all patients presenting multivessel coronary artery disease. Interestingly in this case, the angiographic pattern was normal.

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Banco Invest understanding how to grow in the Portuguese individual clients segment the client analysis

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