Duties to the dead and dying

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Copy of letter from Portuguese congregation, London, to K. K. S. I. regarding re-burial of dead

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Design and development of a self-supported polymer electrolyte fuel cell system with anodic dead-end operation

Design and operational details for a self-supported polymer electrolyte fuel cell (PEFC) system with anodic dead-end fuel supply and internally humidified cathodic oxidant flow are described. During the PEFC operation, nitrogen and water back diffuse across the Nafion membrane from the cathode to the anode and accumulate in the anode flow channels affecting stack performance. The accumulated inert species are flushed from the stack by purging the fuel cell stack with a timer-activated purge valve to address the aforesaid problem. To minimize the system complexity, stack is designed in such a way that all the inert species accumulate in only one cell called the purge cell. A pulsed purge sequence comprises opening the valve for purge duration followed by purge-valve closing for the hold period and repeating the sequence in cycles. Since self-humidification is inadequate to keep the membrane wet, the anodic dead-end-operated PEFC stack with composite membrane comprising perflourosulphonic acid (Nafion) and silica is employed for keeping the membrane humidified even while operating the stack with dry hydrogen and internally humidified air.

Digital Dead Time Logic and Protection Circuitry for PWM Voltage Source Converters

Power semiconductor devices have finite turn on and turn off delays that may not be perfectly matched. In a leg of a voltage source converter, the simultaneous turn on of one device and the turn off of the complementary device will cause a DC bus shoot through, if the turn off delay is larger than the turn on delay time. To avoid this situation it is common practice to blank the two complementary devices in a leg for a small duration of time while switching, which is called dead time. This paper proposes a logic circuit for digital implementation required to control the complementary devices of a leg independently and at the same time preventing cross conduction of devices in a leg, and while providing accurate and stable dead time. This implementation is based on the concept of finite state machines. This circuit can also block improper PWM pulses to semiconductor switches and filters small pulses notches below a threshold time width as the narrow pulses do not provide any significant contribution to average pole voltage, but leads to increased switching loss. This proposed dead time logic has been implemented in a CPLD and is implemented in a protection and delay card for 3- power converters.

Reinforcement learning controllers for automatic generation control in power systems having re-heat units with GRC and dead-band

A new automatic generation controller (AGC) design approach, adopting reinforcement learning (RL) techniques, was recently pro- posed [1]. In this paper we demonstrate the design and performance of controllers based on this RL approach for automatic generation control of systems consisting of units having complex dynamics—the reheat type of thermal units. For such systems, we also assess the capabilities of RL approach in handling realistic system features such as network changes, parameter variations, generation rate constraint (GRC), and governor deadband.

Experimental Study on Dead-Time Induced Oscillations in a 100-kW Open-Loop Induction Motor Drive

This paper reports instability and oscillations in the stator current under light-load conditions in a practical 100-kW induction motor drive. Dead-time is shown to be a cause for such oscillations. This paper shows experimentally that these oscillations could be mitigated significantly with the help of a simple dead-time compensation scheme.

Study on the Effect of Dead Time and its Compensation for Bus-Clamping PWM Techniques

Dead-time is provided in between the gating signals of the top and bottom semiconductor switches in an inverter leg to prevent the shorting of DC bus. Due to this dead time, there is a significant unwanted change in the output voltage of the inverter. The effect is different for different pulse width modulation (PWM) methodologies. The effect of dead-time on the output fundamental voltage is studied theoretically as well as experimentally for bus-clamping PWM methodologies. Further, experimental observations on the effectiveness of dead-time compensation are presented.

Average Modelling of a Voltage Source Inverter with Dead-Time in a Synchronous Reference Frame

Voltage source inverters are an integral part of renewable power sources and smart grid systems. Computationally efficient and fairly accurate models for the voltage source inverter are required to carry out extensive simulation studies on complex power networks. Accuracy requires that the effect of dead-time be incorporated in the inverter model. The dead-time is essentially a short delay introduced between the gating pulses to the complementary switches in an inverter leg for the safety of power devices. As the modern voltage source inverters switch at fairly high frequencies, the dead-time significantly influences the output fundamental voltage. Dead-time also causes low-frequency harmonic distortion and is hence important from a power quality perspective. This paper studies the dead-time effect in a synchronous dq reference frame, since dynamic studies and controller design are typically carried out in this frame of reference. For the sake of computational efficiency, average models are derived, incorporating the dead-time effect, in both RYB and dq reference frames. The average models are shown to consume less computation time than their corresponding switching models, the accuracies of the models being comparable. The proposed average synchronous reference frame model, including effect of dead-time, is validated through experimental results.

Experimental Study on Dead-Time Induced Oscillations in a 100-kW Open-Loop Induction Motor Drive

This paper reports instability and oscillations in the stator current under light-load conditions in a practical 100-kW induction motor drive. Dead-time is shown to be a cause for such oscillations. This paper shows experimentally that these oscillations could be mitigated significantly with the help of a simple dead-time compensation scheme.

An Improved Dead-Time Compensation Scheme for Voltage Source Inverters Considering the Device Switching Transition Times

Inverter dead-time, which is meant to prevent shoot-through fault, causes harmonic distortion and change in the fundamental voltage in the inverter output. Typical dead-time compensation schemes ensure that the amplitude of the fundamental output current is as desired, and also improve the current waveform quality significantly. However, even with compensation, the motor line current waveform is observed to be distorted close to the current zero-crossings. The IGBT switching transition times being significantly longer at low currents than at high currents is an important reason for this zero-crossover distortion. Hence, this paper proposes an improved dead-time compensation scheme, which makes use of the measured IGBT switching transition times at low currents. Measured line current waveforms in a 2.2 kW induction motor drive with the proposed compensation scheme are compared against those with the conventional dead-time compensation scheme and without dead-time compensation. The experimental results on the motor drive clearly demonstrate the improvement in the line current waveform quality with the proposed method.

Small-Signal Stability Analysis of an Open-loop Induction Motor Drive Including the Effect of Inverter Dead-Time

This paper demonstrates light-load instability in open-loop induction motor drives on account of inverter dead-time. The dynamic equations of an inverter fed induction motor, incorporating the effect of dead-time, are considered. A procedure to derive the small-signal model of the motor, including the effect of inverter dead-time, is presented. Further, stability analysis is carried out on a 100-kW, 415V, 3-phase induction motor considering no-load. For voltage to frequency (i.e. V/f) ratios between 0.5 and 1 pu, the analysis brings out regions of instability on the V-f plane, in the frequency range between 5Hz and 20Hz. Simulation and experimental results show sub-harmonic oscillations in the motor current in this region, confirming instability as predicted by the analysis.

An Advanced Gate Driver for Insulated Gate Bipolar Transistors to Eliminate Dead-time Induced Distortions in Inverter Output

Dead-time is introduced between the gating signals to the top and bottom switches in a voltage source inverter (VSI) leg, to prevent shoot through fault due to the finite turn-off times of IGBTs. The dead-time results in a delay when the incoming device is an IGBT, resulting in error voltage pulses in the inverter output voltage. This paper presents the design, fabrication and testing of an advanced gate driver, which eliminates dead-time and consequent output distortion. Here, the gating pulses are generated such that the incoming IGBT transition is not delayed and shoot-through is also prevented. The various logic units of the driver card and fault tolerance of the driver are verified through extensive tests on different topologies such as chopper, half-bridge and full-bridge inverter, and also at different conditions of load. Experimental results demonstrate the improvement in the load current waveform quality with the proposed circuit, on account of elimination of dead-time.

Optimization of bus allocation to depots by minimizing dead kilometers

In metropolitan cities, public transportation service plays a vital role in mobility of people, and it has to introduce new routes more frequently due to the fast development of the city in terms of population growth and city size. Whenever there is introduction of new route or increase in frequency of buses, the nonrevenue kilometers covered by the buses increases as depot and route starting/ending points are at different places. This non-revenue kilometers or dead kilometers depends on the distance between depot and route starting point/ending point. The dead kilometers not only results in revenue loss but also results in an increase in the operating cost because of the extra kilometers covered by buses. Reduction of dead kilometers is necessary for the economic growth of the public transportation system. Therefore, in this study, the attention is focused on minimizing dead kilometers by optimizing allocation of buses to depots depending upon the shortest distance between depot and route starting/ending points. We consider also depot capacity and time period of operation during allocation of buses to ensure parking safety and proper maintenance of buses. Mathematical model is developed considering the aforementioned parameters, which is a mixed integer program, and applied to Bangalore Metropolitan Transport Corporation (BMTC) routes operating presently in order to obtain optimal bus allocation to depots. Database for dead kilometers of depots in BMTC for all the schedules are generated using the Form-4 (trip sheet) of each schedule to analyze depot-wise and division-wise dead kilometers. This study also suggests alternative locations where depots can be located to reduce dead kilometers. Copyright (C) 2015 John Wiley & Sons, Ltd.

Modelling and analysis of an open-loop induction motor drive incorporating the effect of inverter dead-time

The objective of this paper is to study the influence of inverter dead-time on steady as well as dynamic operation of an open-loop induction motor drive fed from a voltage source inverter (VSI). Towards this goal, this paper presents a systematic derivation of a dynamic model for an inverter-fed induction motor, incorporating the effect of inverter dead-time, in the synchronously revolving dq reference frame. Simulation results based on this dynamic model bring out the impact of inverter dead-time on both the transient response and steady-state operation of the motor drive. For the purpose of steady-state analysis, the dynamic model of the motor drive is used to derive a steady-state model, which is found to be non-linear. The steady-state model shows that the impact of dead-time can be seen as an additional resistance in the stator circuit, whose value depends on the stator current. Towards precise evaluation of this dead-time equivalent resistance, an analytical expression is proposed for the same in terms of inverter dead-time, switching frequency, modulation index and load impedance. The notion of dead-time equivalent resistance is shown to simplify the solution of the non-linear steady-state model. The analytically evaluated steady-state solutions are validated through numerical simulations and experiments.

Peftjauawybast, king of Nen-nesut : genealogy, art history, and the chronology of late libyan Egypt

This paper argues in detail for the identification of Peftjauawybast, King of Nen-nesut (fl. 728/720 BC ), with Peftjauawybast, High Priest of Ptah in Memphis (fl. c. 790–780 BC2), known from the Apis stela of year 28 of Shoshenq III. This identification ties in with a significant lowering of the accepted dates for the kings from Shoshenq III, Osorkon III and Takeloth III to Shoshenq V, and the material culture associated with them. Such a shift seems to be supported by stylistic and genealogical evidence. As a consequence, it is further suggested that the Master of Shipping at Nen-nesut, Pediese i, was perhaps related by descent and marriage to the family of the High Priests of Memphis and King Peftjauawybast.