Mecanismo de tolerância a falhas através de escalonamento para uma arquitetura reconfigurável de grão grosso

The continuous evolution of integrated circuit technology has allowed integrating thousands of transistors on a single chip. This is due to the miniaturization process, which reduces the diameter of wires and transistors. One drawback of this process is that the circuit becomes more fragile and susceptible to break, making the circuit more susceptible to permanent faults during the manufacturing process as well as during their lifetime. Coarse Grained Reconfigurable Architectures (CGRAs) have been used as an alternative to traditional architectures in an attempt to tolerate such faults due to its intrinsic hardware redundancy and high performance. This work proposes a fault tolerance mechanism in a CGRA in order to increase the architecture fault tolerance even considering a high fault rate. The proposed mechanism was added to the scheduler, which is the mechanism responsible for mapping instructions onto the architecture. The instruction mapping occurs at runtime, translating binary code without the need for recompilation. Furthermore, to allow faster implementation, instruction mapping is performed using a greedy module scheduling algorithm, which consists of a software pipeline technique for loop acceleration. The results show that, even with the proposed mechanism, the time for mapping instructions is still in order of microseconds. This result allows that instruction mapping process remains at runtime. In addition, a study was also carried out mapping scheduler rate. The results demonstrate that even at fault rates over 50% in functional units and interconnection components, the scheduler was able to map instructions onto the architecture in most of the tested applications.

Efeitos da internacionalização no desvio da estrutura de capital alvo e na velocidade de ajuste

This dissertation investigates the effects of internationalization in two gaps related to the capital structure that have not been discussed by the Brazilian literature yet. To this, were developed two independent sections. The first examined what the effects of internationalization on the deviation from the target capital structure. The second examined what the effects of internationalization on speed of adjustment (SOA) of the capital structure. It used data from Brazil, multinational and domestic companies, from 2006 to 2014. The results of the first analysis indicate that internationalization helps reduce the difference between the target and the current debt. That is, to the extent that the level of internationalization increases; whether only export or a combination of export, assets and employees abroad, the gap between the current structure and the target structure decreases. This reduction is given as a function of internationalization as a consequence of the upstream effect of the upstream-downstream hypothesis. Thus, as the Market Timing theory, it can be seen as an opportunity for adjustment of the capital structure, and with the reduction of deviation, there is also a reduction in the cost of capital of the firm. The result of the second analysis indicates that internationalization is able to significantly increase the speed adjustment, ensuring for the multinational a faster adjustment of its capital structure. Exports increase the SOA in 9 to 23%. And when also kept active assets and employees abroad the increase is 8 to 20%. In terms of time, while domestic company takes more than three years to reduce half of the deviation that has, while multinacional companies take on average one and a half year to reduce the same proportion of the deviation. The validity of the upstream-downstream hypothesis for the effect of internationalization in SOA was confirmed by comparing the results for US companies. Thus, the phenomenon of internationalization increases SOA when companies are from less stable markets, such as Brazil; and it has a less significcative effect when companies are derived from more stable markets, because they already have a high speed of adjustmennt. In addition, the adequacy analysis of the estimators also showed the model pooled OLS (Ordinary Least Squares) presents the highest quality in predicting the SOA than the system GMM (Generalized Method of Moments). For future studies it is suggested to analyze the effect of international event, by itself, and to validate the hypothesis using samples of different markets and the use of other estimators.

Qual a contribuição das características antropométricas na velocidade de corrida de curta distância ?

v. 19, n. 2, abr./jun. 2016.

Avances en algoritmos de estimación de distribuciones. Alternativas en el aprendizaje y representación de problemas

131 p.: graf.

Tecnologías actuales para dispositivos lógicos programables

Gran parte de los circuitos integrados de aplicación específica actuales se desarrollan sobre dispositivos lógicos programables (PLD). Los fabricantes ofrecen diferentes tecnologías programables, algunas de ellas admiten la reconfiguración de los diseños, incluso en tiempo de operación, mientras que otras pueden configurarse una única vez (tecnologías fusibles y antifusibles). En el trabajo se analizarán las diferentes familias de dispositivos y sus tecnologías, con especial atención en su capacidad de integración y consumo. Asimismo se realizarán diseños simples con alguna de ellas.

Zirkuitu integratuak: telekomunikazio ingeniaritza

174 p.

Marco-reloj-despertador basado en FPGA

Gordon E. Moore, cofundador de Intel, predijo en una publicación del año 1965 que aproximadamente cada dos años se duplicaría el número de transistores presentes en un circuito integrado, debido a las cada vez mejores tecnologías presentes en el proceso de elaboración [1]. A esta ley se la conoce como Ley de Moore y su cumplimiento se ha podido constatar hasta hoy en día. Gracias a ello, con el paso del tiempo cada vez se presentan en el mercado circuitos integrados más potentes, con mayores prestaciones para realizar tareas cada vez más complejas. Un tipo de circuitos integrados que han podido evolucionar de forma importante son los dispositivos de lógica programable, circuitos integrados que permiten implementar sobre ellos las funciones lógicas deseadas. Hasta hace no muchos años, dichos dispositivos eran capaces de incorporar circuitos compuestos por unas pocas funciones lógicas, pero gracias al proceso de miniaturización predicho por la Ley de Moore, hoy en día son capaces de implementar circuitos tan complejos como puede ser un microprocesador; dichos dispositivos reciben el nombre de FPGA, siglas de Field Programmable Gate Array. El presente proyecto tiene como objetivo construir un marco de fotos digital con reloj y despertador programable, valiéndose para ello de la FPGA Cyclone II de Altera y una pantalla táctil de la casa Terasic. Con este fin, se documentará en primera instancia los dispositivos a utilizar con sus características y posibilidades que plantean, para pasar posteriormente al diseño de la aplicación y su implementación e integración en la placa para comprobar su correcto funcionamiento.

Generación automática de VHDL mediante Simulink HDL coder y aplicación al procesado de señales

Gordon E. Moore, co-fundador de Intel, predijo en una publicación del año 1965 que aproximadamente cada dos años se duplicaría el número de transistores presentes en un circuito integrado, debido a las cada vez mejores tecnologías presentes en el proceso de elaboración. A esta ley se la conoce como Ley de Moore y su cumplimiento se ha podido constatar hasta hoy en día. Gracias a ello, con el paso del tiempo cada vez se presentan en el mercado circuitos integrados más potentes, con mayores prestaciones para realizar tareas cada vez más complejas. Un tipo de circuitos integrados que han podido evolucionar de forma importante por dicho motivo, son los dispositivos de lógica programable, circuitos integrados que permiten implementar sobre ellos las funciones lógicas que desee implementar el usuario. Hasta hace no muchos años, dichos dispositivos eran capaces de implementar circuitos compuestos por unas pocas funciones lógicas, pero gracias al proceso de miniaturización predicho por la Ley de Moore, hoy en día son capaces de implementar circuitos tan complejos como puede ser un microprocesador; dichos dispositivos reciben el nombre de FPGA, siglas de Field Programmable Gate Array. Debido a la mayor capacidad y por lo tanto a diseños más complejos implementados sobre las FPGA, en los últimos años han aparecido herramientas cuyo objetivo es hacer más fácil el proceso de ingeniería dentro de un desarrollo en este tipo de dispositivos, como es la herramienta HDL Coder de la compañía MathWorks, creadores también Matlab y Simulink, unas potentes herramientas usadas ampliamente en diferentes ramas de la ingeniería. El presente proyecto tiene como objetivo evaluar el uso de dicha herramienta para el procesado digital de señales, usando para ello una FPGA Cyclone II de la casa Altera. Para ello, se empezará analizando la herramienta escogida comparándola con herramientas de la misma índole, para a continuación seleccionar una aplicación de procesado digital de señal a implementar. Tras diseñar e implementar la aplicación escogida, se deberá simular en PC para finalmente integrarla en la placa de evaluación seleccionada y comprobar su correcto funcionamiento. Tras analizar los resultados de la aplicación de implementada, concretamente un analizador de la frecuencia fundamental de una señal de audio, se ha comprobado que la herramienta HDL Coder, es adecuada para este tipo de desarrollos, facilitando enormemente los procesos tanto de implementación como de validación gracias al mayor nivel de abstracción que aporta.

Formulações nanobiotecnológicas para vetorização da Curcumina e seus derivados

Projeto de Pós-Graduação/Dissertação apresentado à Universidade Fernando Pessoa como parte dos requisitos para obtenção do grau de Mestre em Ciências Farmacêuticas

Advanced energy efficient coordinated multi-point transmission for OFDMA

The ever-growing energy consumption in mobile networks stimulated by the expected growth in data tra ffic has provided the impetus for mobile operators to refocus network design, planning and deployment towards reducing the cost per bit, whilst at the same time providing a signifi cant step towards reducing their operational expenditure. As a step towards incorporating cost-eff ective mobile system, 3GPP LTE-Advanced has adopted the coordinated multi-point (CoMP) transmission technique due to its ability to mitigate and manage inter-cell interference (ICI). Using CoMP the cell average and cell edge throughput are boosted. However, there is room for reducing energy consumption further by exploiting the inherent exibility of dynamic resource allocation protocols. To this end packet scheduler plays the central role in determining the overall performance of the 3GPP longterm evolution (LTE) based on packet-switching operation and provide a potential research playground for optimizing energy consumption in future networks. In this thesis we investigate the baseline performance for down link CoMP using traditional scheduling approaches, and subsequently go beyond and propose novel energy e fficient scheduling (EES) strategies that can achieve power-e fficient transmission to the UEs whilst enabling both system energy effi ciency gain and fairness improvement. However, ICI can still be prominent when multiple nodes use common resources with di fferent power levels inside the cell, as in the so called heterogeneous networks (Het- Net) environment. HetNets are comprised of two or more tiers of cells. The rst, or higher tier, is a traditional deployment of cell sites, often referred to in this context as macrocells. The lower tiers are termed small cells, and can appear as microcell, picocells or femtocells. The HetNet has attracted signiffi cant interest by key manufacturers as one of the enablers for high speed data at low cost. Research until now has revealed several key hurdles that must be overcome before HetNets can achieve their full potential: bottlenecks in the backhaul must be alleviated, as well as their seamless interworking with CoMP. In this thesis we explore exactly the latter hurdle, and present innovative ideas on advancing CoMP to work in synergy with HetNet deployment, complemented by a novel resource allocation policy for HetNet tighter interference management. As system level simulator has been used to analyze the proposed algorithm/protocols, and results have concluded that up to 20% energy gain can be observed.

Ferroelectric : CNTs structures fabrication for advanced functional nano devices

This work is about the combination of functional ferroelectric oxides with Multiwall Carbon Nanotubes for microelectronic applications, as for example potential 3 Dimensional (3D) Non Volatile Ferroelectric Random Access Memories (NVFeRAM). Miniaturized electronics are ubiquitous now. The drive to downsize electronics has been spurred by needs of more performance into smaller packages at lower costs. But the trend of electronics miniaturization challenges board assembly materials, processes, and reliability. Semiconductor device and integrated circuit technology, coupled with its associated electronic packaging, forms the backbone of high-performance miniaturized electronic systems. However, as size decreases and functionalization increases in the modern electronics further size reduction is getting difficult; below a size limit the signal reliability and device performance deteriorate. Hence miniaturization of siliconbased electronics has limitations. On this background the Road Map for Semiconductor Industry (ITRS) suggests since 2011 alternative technologies, designated as More than Moore; being one of them based on carbon (carbon nanotubes (CNTs) and graphene) [1]. CNTs with their unique performance and three dimensionality at the nano-scale have been regarded as promising elements for miniaturized electronics [2]. CNTs are tubular in geometry and possess a unique set of properties, including ballistic electron transportation and a huge current caring capacity, which make them of great interest for future microelectronics [2]. Indeed CNTs might have a key role in the miniaturization of Non Volatile Ferroelectric Random Access Memories (NVFeRAM). Moving from a traditional two dimensional (2D) design (as is the case of thin films) to a 3D structure (based on a tridimensional arrangement of unidimensional structures) will result in the high reliability and sensing of the signals due to the large contribution from the bottom electrode. One way to achieve this 3D design is by using CNTs. Ferroelectrics (FE) are spontaneously polarized and can have high dielectric constants and interesting pyroelectric, piezoelectric, and electrooptic properties, being a key application of FE electronic memories. However, combining CNTs with FE functional oxides is challenging. It starts with materials compatibility, since crystallization temperature of FE and oxidation temperature of CNTs may overlap. In this case low temperature processing of FE is fundamental. Within this context in this work a systematic study on the fabrication of CNTs - FE structures using low cost low temperature methods was carried out. The FE under study are comprised of lead zirconate titanate (Pb1-xZrxTiO3, PZT), barium titanate (BaTiO3, BT) and bismuth ferrite (BiFeO3, BFO). The various aspects related to the fabrication, such as effect on thermal stability of MWCNTs, FE phase formation in presence of MWCNTs and interfaces between the CNTs/FE are addressed in this work. The ferroelectric response locally measured by Piezoresponse Force Microscopy (PFM) clearly evidenced that even at low processing temperatures FE on CNTs retain its ferroelectric nature. The work started by verifying the thermal decomposition behavior under different conditions of the multiwall CNTs (MWCNTs) used in this work. It was verified that purified MWCNTs are stable up to 420 ºC in air, as no weight loss occurs under non isothermal conditions, but morphology changes were observed for isothermal conditions at 400 ºC by Raman spectroscopy and Transmission Electron Microscopy (TEM). In oxygen-rich atmosphere MWCNTs started to oxidized at 200 ºC. However in argon-rich one and under a high heating rate MWCNTs remain stable up to 1300 ºC with a minimum sublimation. The activation energy for the decomposition of MWCNTs in air was calculated to lie between 80 and 108 kJ/mol. These results are relevant for the fabrication of MWCNTs – FE structures. Indeed we demonstrate that PZT can be deposited by sol gel at low temperatures on MWCNTs. And particularly interesting we prove that MWCNTs decrease the temperature and time for formation of PZT by ~100 ºC commensurate with a decrease in activation energy from 68±15 kJ/mol to 27±2 kJ/mol. As a consequence, monophasic PZT was obtained at 575 ºC for MWCNTs - PZT whereas for pure PZT traces of pyrochlore were still present at 650 ºC, where PZT phase formed due to homogeneous nucleation. The piezoelectric nature of MWCNTs - PZT synthesised at 500 ºC for 1 h was proved by PFM. In the continuation of this work we developed a low cost methodology of coating MWCNTs using a hybrid sol-gel / hydrothermal method. In this case the FE used as a proof of concept was BT. BT is a well-known lead free perovskite used in many microelectronic applications. However, synthesis by solid state reaction is typically performed around 1100 to 1300 ºC what jeopardizes the combination with MWCNTs. We also illustrate the ineffectiveness of conventional hydrothermal synthesis in this process due the formation of carbonates, namely BaCO3. The grown MWCNTs - BT structures are ferroelectric and exhibit an electromechanical response (15 pm/V). These results have broad implications since this strategy can also be extended to other compounds of materials with high crystallization temperatures. In addition the coverage of MWCNTs with FE can be optimized, in this case with non covalent functionalization of the tubes, namely with sodium dodecyl sulfate (SDS). MWCNTs were used as templates to grow, in this case single phase multiferroic BFO nanorods. This work shows that the use of nitric solvent results in severe damages of the MWCNTs layers that results in the early oxidation of the tubes during the annealing treatment. It was also observed that the use of nitric solvent results in the partial filling of MWCNTs with BFO due to the low surface tension (<119 mN/m) of the nitric solution. The opening of the caps and filling of the tubes occurs simultaneously during the refluxing step. Furthermore we verified that MWCNTs have a critical role in the fabrication of monophasic BFO; i.e. the oxidation of CNTs during the annealing process causes an oxygen deficient atmosphere that restrains the formation of Bi2O3 and monophasic BFO can be obtained. The morphology of the obtained BFO nano structures indicates that MWCNTs act as template to grow 1D structure of BFO. Magnetic measurements on these BFO nanostructures revealed a week ferromagnetic hysteresis loop with a coercive field of 956 Oe at 5 K. We also exploited the possible use of vertically-aligned multiwall carbon nanotubes (VA-MWCNTs) as bottom electrodes for microelectronics, for example for memory applications. As a proof of concept BiFeO3 (BFO) films were in-situ deposited on the surface of VA-MWCNTs by RF (Radio Frequency) magnetron sputtering. For in situ deposition temperature of 400 ºC and deposition time up to 2 h, BFO films cover the VA-MWCNTs and no damage occurs either in the film or MWCNTs. In spite of the macroscopic lossy polarization behaviour, the ferroelectric nature, domain structure and switching of these conformal BFO films was verified by PFM. A week ferromagnetic ordering loop was proved for BFO films on VA-MWCNTs having a coercive field of 700 Oe. Our systematic work is a significant step forward in the development of 3D memory cells; it clearly demonstrates that CNTs can be combined with FE oxides and can be used, for example, as the next 3D generation of FERAMs, not excluding however other different applications in microelectronics.

Análise do transporte ferroviário de mercadorias associado à problemática da diferença de bitola entre linhas da rede ferroviária: estudo do caso prático: ligação do porto de Aveiro ao corredor internacional de mercadorias E-80

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Civil

Estudo de viabilidade de utilização de VLC em infra-estruturas ITS baseadas em semáforos rodoviários a LEDs

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

Melhoria da eficiência de amplificadores de potência para sinais RF com envolvente variável

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Electrónica e Telecomunicações

Avaliação do comportamento e reforço da Ponte de Maçaínhas sob a ação do tráfego ferroviário

A presente dissertação tem como principal objetivo a avaliação do estado de conservação de uma ponte ferroviária metálica centenária para posteriormente se efetuar o reforço desta. O objeto de estudo foi a Ponte de Maçaínhas, uma ponte metálica treliçada que se situa na linha da Beira Baixa permitindo a ligação entre a Guarda e a Covilhã. Este trabalho envolveu um estudo profundo de vários conteúdos normativos relativos a ações em pontes ferroviárias e ações ambientais. Este estudo estende-se ainda ao campo das verificações regulamentares e critérios de segurança estrutural adequadas ao presente contexto. A operação de reforço começou numa rigorosa análise dos componentes estruturais da ponte, através do estudo de plantas e de um extenso registo fotográfico, para posteriormente se conceber um modelo numérico que traduzisse a situação real. Ao modelo concebido foram aplicadas as cargas regulamentares adequadas por forma a entender o comportamento que a ponte apresenta perante estas e se as suas secções transversais apresentam capacidade resistente suficiente. Caso estas não apresentem capacidade resistente suficiente teriam de ser intervencionadas. Concluído o processo de avaliação estrutural e de reforço, procedeu-se à verificação do comportamento da estrutura reforçada perante as ações de projeto. Com isto pretende-se avaliar se os esforços se distribuem da mesma maneira ou se a operação de reforço teve algum efeito na distribuição destes. Por último, para avaliar o comportamento da estrutura perante a passagem de tráfego real, realizaram-se análises dinâmicas que tiveram por base um grupo de veículos que habitualmente circulam na linha da Beira Baixa e um comboio de alta velocidade. Estas análises foram realizadas tanto para a situação pré reforço como pós reforço. Desta forma conseguiu-se fazer um paralelo entre ambas as condições e perceber se a operação de reforço foi bem-sucedida.