Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Design and optimization of FinFETs for ultra-low-voltage analog applications

In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic de gain (A(vo)) and cutoff frequency (f(T)) for 60 and 30 nm FinFETs operated at low drive current (J(ds) = 5 mu A/mu m). The improved Avo and fT are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

Source/drain extension region engineering in FinFETs for low-voltage analog applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.

Analog performance of double gate SOI transistors

Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L-G reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f(T) and f(max) to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its fT was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted fmax in SG SOI was higher (similar to 40%) compared to DGSOI due to its lower capacitance.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DC devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut-off frequency (f(T)) and intrinsic voltage gain (A(VO)). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate-underlap DG MOSFETs. (C) 2008 Elsevier Ltd. All rights reserved.

Antimicrobial/cytolytic peptides from the venom of the North African scorpion, Androctonus amoreuxi: Biochemical and functional characterization of natural peptides and a single site-substituted analog

The venoms of scorpions are complex cocktails of polypeptide toxins that fall into two structural categories: those that contain cysteinyl residues with associated disulfide bridges and those that do not. As the majority of lethal toxins acting upon ion channels fall into the first category, most research has been focused there. Here we report the identification and structural characterization of two novel 18-mer antimicrobial peptides from the venom of the North African scorpion, Androctonus amoreuxi. Named AamAP1 and AamAP2, both peptides are C-terminally amidated and differ in primary structure at just two sites: Leu?Pro at position 2 and Phe?Ile at position 17. Synthetic replicates of both peptides exhibited a broad-spectrum of antimicrobial activity against a Gram-positive bacterium (Staphylococcus aureus), a Gram-negative bacterium (Escherichia coli) and a yeast (Candida albicans), at concentrations ranging between 20µM and 150µM. In this concentration range, both peptides produced significant degrees of hemolysis. A synthetic replicate of AamAP1 containing a single substitution (His?Lys) at position 8, generated a peptide (AamAP-S1) with enhanced antimicrobial potency (3-5µM) against the three test organisms and within this concentration range, hemolytic effects were negligible. In addition, this His?Lys variant exhibited potent growth inhibitory activity (ID(50) 25-40µm) against several human cancer cell lines and endothelial cells that was absent in both natural peptides. Natural bioactive peptide libraries, such as those that occur in scorpion venoms, thus constitute a unique source of novel lead compounds with drug development potential whose biological properties can be readily manipulated by simple synthetic chemical means.

Analog of Rabi oscillations in resonant electron-ion systems

Quantum coherence between electron and ion dynamics, observed in organic semiconductors by means of ultrafast spectroscopy, is the object of recent theoretical and computational studies. To simulate this kind of quantum coherent dynamics, we have introduced in a previous article [L. Stella, M. Meister, A. J. Fisher, and A. P. Horsfield, J. Chem. Phys. 127, 214104 (2007)] an improved computational scheme based on Correlated Electron-Ion Dynamics (CEID). In this article, we provide a generalization of that scheme to model several ionic degrees of freedom and many-body electronic states. To illustrate the capability of this extended CEID, we study a model system which displays the electron-ion analog of the Rabi oscillations. Finally, we discuss convergence and scaling properties of the extended CEID along with its applicability to more realistic problems. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3589165]