Defect production in silicon carbide irradiated with Ne and Xe ions with energy of 2.3 MeV/amu

In the present work specimens of mono-crystalline silicon carbide (4H polytype) were irradiated to three successively increasing ion fluences ranging from 7.2 x 10(14) to 6.0 x 10(16) ions/cm(2) (corresponding to the peak displacement damage of 1, 4 and 13 dpa) with Ne and Xe ions respectively with the energy of 2.3 MeV/amu. The irradiated specimens were subsequently annealed at temperatures of 1173 and 1273 K. Defect structure was investigated with transmission electron microscopy (TEM) using a cross-sectional specimen preparation technique. The typical microstructures of the annealed specimens irradiated with Ne or Xe ions to high fluences are characterized by small gas bubbles in high concentration in the peak damage region and black dots and dislocation loops (located in the basal plane) in a shallower and broader depth region. Larger dislocation loops were observed in the Xe-ion irradiated specimen than in the Ne-ion irradiated specimen at the same peak damage level. The enhanced formation of dislocation loops in the case of Xe-ion irradiation is understandable by assuming stronger inclination of heavier inert-gas atoms to occupy substitute site in the peak damage region.

Sol-Gel Alumina Nano Composites for Functional Applications

The thesis entitled "Sol-Gel Alumina Nano Composites for Functional Applications" investigate sol-gel methods of synthesis of alumina nanocomposites special reference to alumina-aluminium titanate and alumina-lanthanum phosphate composites. The functional properties such as thermal expansion coefficient and thermal shock resistance, machinability of composites as well as thermal protection are highlighted in addition to novel approach in synthesis of composites.A general introduction of alumina matrix composites materials, followed by brief coverage of alumina-aluminium titanate and alumina-lanthanum phosphate composites is highlight of the first chapter. The second chapter deals with the sol-gel synthesis of aluminium titanate and alumina-aluminium titanate composite. The synthesis of machinable substrate, based on alumina and lanthanum phosphate forms the basis of the third chapter. The fourth chapter describes the sol-gel coating of mullite on SiC substrate for the possible gas filtration application.

Growth and Characterization of Silicon Carbide Thin Films Using a Nontraditional Hollow Cathode Sputtering Technique

Silicon carbide (SiC) is considered a suitable candidate for high-power, high-frequency devices due to its wide bandgap, high breakdown field, and high electron mobility. It also has the unique ability to synthesize graphene on its surface by subliming Si during an annealing stage. The deposition of SiC is most often carried out using chemical vapor deposition (CVD) techniques, but little research has been explored with respect to the sputtering of SiC. Investigations of the thin film depositions of SiC from pulse sputtering a hollow cathode SiC target are presented. Although there are many different polytypes of SiC, techniques are discussed that were used to identify the film polytype on both 4H-SiC substrates and Si substrates. Results are presented about the ability to incorporate Ge into the growing SiC films for the purpose of creating a possible heterojunction device with pure SiC. Efforts to synthesize graphene on these films are introduced and reasons for the inability to create it are discussed. Analysis mainly includes crystallographic and morphological studies about the deposited films and their quality using x-ray diffraction (XRD), reflection high energy electron diffraction (RHEED), transmission electron microscopy (TEM), scanning electron microscopy (SEM), atomic force microscopy (AFM), Auger electron spectroscopy (AES) and Raman spectroscopy. Optical and electrical properties are also discussed via ellipsometric modeling and resistivity measurements. The general interpretation of these analytical experiments indicates that the films are not single crystal. However, the majority of the films, which proved to be the 3C-SiC polytype, were grown in a highly ordered and highly textured manner on both (111) and (110) Si substrates.

Technology and characterization of GaN-HEMTs devices: high temperature and trapping effects

Los transistores de alta movilidad electrónica basados en GaN han sido objeto de una extensa investigación ya que tanto el GaN como sus aleaciones presentan unas excelentes propiedades eléctricas (alta movilidad, elevada concentración de portadores y campo eléctrico crítico alto). Aunque recientemente se han incluido en algunas aplicaciones comerciales, su expansión en el mercado está condicionada a la mejora de varios asuntos relacionados con su rendimiento y habilidad. Durante esta tesis se han abordado algunos de estos aspectos relevantes; por ejemplo, la fabricación de enhancement mode HEMTs, su funcionamiento a alta temperatura, el auto calentamiento y el atrapamiento de carga. Los HEMTs normalmente apagado o enhancement mode han atraído la atención de la comunidad científica dedicada al desarrollo de circuitos amplificadores y conmutadores de potencia, ya que su utilización disminuiría significativamente el consumo de potencia; además de requerir solamente una tensión de alimentación negativa, y reducir la complejidad del circuito y su coste. Durante esta tesis se han evaluado varias técnicas utilizadas para la fabricación de estos dispositivos: el ataque húmedo para conseguir el gate-recess en heterostructuras de InAl(Ga)N/GaN; y tratamientos basados en flúor (plasma CF4 e implantación de F) de la zona debajo de la puerta. Se han llevado a cabo ataques húmedos en heteroestructuras de InAl(Ga)N crecidas sobre sustratos de Si, SiC y zafiro. El ataque completo de la barrera se consiguió únicamente en las muestras con sustrato de Si. Por lo tanto, se puede deducir que la velocidad de ataque depende de la densidad de dislocaciones presentes en la estructura, ya que el Si presenta un peor ajuste del parámetro de red con el GaN. En relación a los tratamientos basados en flúor, se ha comprobado que es necesario realizar un recocido térmico después de la fabricación de la puerta para recuperar la heteroestructura de los daños causados durante dichos tratamientos. Además, el estudio de la evolución de la tensión umbral con el tiempo de recocido ha demostrado que en los HEMTs tratados con plasma ésta tiende a valores más negativos al aumentar el tiempo de recocido. Por el contrario, la tensión umbral de los HEMTs implantados se desplaza hacia valores más positivos, lo cual se atribuye a la introducción de iones de flúor a niveles más profundos de la heterostructura. Los transistores fabricados con plasma presentaron mejor funcionamiento en DC a temperatura ambiente que los implantados. Su estudio a alta temperatura ha revelado una reducción del funcionamiento de todos los dispositivos con la temperatura. Los valores iniciales de corriente de drenador y de transconductancia medidos a temperatura ambiente se recuperaron después del ciclo térmico, por lo que se deduce que dichos efectos térmicos son reversibles. Se han estudiado varios aspectos relacionados con el funcionamiento de los HEMTs a diferentes temperaturas. En primer lugar, se han evaluado las prestaciones de dispositivos de AlGaN/GaN sobre sustrato de Si con diferentes caps: GaN, in situ SiN e in situ SiN/GaN, desde 25 K hasta 550 K. Los transistores con in situ SiN presentaron los valores más altos de corriente drenador, transconductancia, y los valores más bajos de resistencia-ON, así como las mejores características en corte. Además, se ha confirmado que dichos dispositivos presentan gran robustez frente al estrés térmico. En segundo lugar, se ha estudiado el funcionamiento de transistores de InAlN/GaN con diferentes diseños y geometrías. Dichos dispositivos presentaron una reducción casi lineal de los parámetros en DC en el rango de temperaturas de 25°C hasta 225°C. Esto se debe principalmente a la dependencia térmica de la movilidad electrónica, y también a la reducción de la drift velocity con la temperatura. Además, los transistores con mayores longitudes de puerta mostraron una mayor reducción de su funcionamiento, lo cual se atribuye a que la drift velocity disminuye más considerablemente con la temperatura cuando el campo eléctrico es pequeño. De manera similar, al aumentar la distancia entre la puerta y el drenador, el funcionamiento del HEMT presentó una mayor reducción con la temperatura. Por lo tanto, se puede deducir que la degradación del funcionamiento de los HEMTs causada por el aumento de la temperatura depende tanto de la longitud de la puerta como de la distancia entre la puerta y el drenador. Por otra parte, la alta densidad de potencia generada en la región activa de estos transistores conlleva el auto calentamiento de los mismos por efecto Joule, lo cual puede degradar su funcionamiento y Habilidad. Durante esta tesis se ha desarrollado un simple método para la determinación de la temperatura del canal basado en medidas eléctricas. La aplicación de dicha técnica junto con la realización de simulaciones electrotérmicas han posibilitado el estudio de varios aspectos relacionados con el autocalentamiento. Por ejemplo, se han evaluado sus efectos en dispositivos sobre Si, SiC, y zafiro. Los transistores sobre SiC han mostrado menores efectos gracias a la mayor conductividad térmica del SiC, lo cual confirma el papel clave que desempeña el sustrato en el autocalentamiento. Se ha observado que la geometría del dispositivo tiene cierta influencia en dichos efectos, destacando que la distribución del calor generado en la zona del canal depende de la distancia entre la puerta y el drenador. Además, se ha demostrado que la temperatura ambiente tiene un considerable impacto en el autocalentamiento, lo que se atribuye principalmente a la dependencia térmica de la conductividad térmica de las capas y sustrato que forman la heterostructura. Por último, se han realizado numerosas medidas en pulsado para estudiar el atrapamiento de carga en HEMTs sobre sustratos de SiC con barreras de AlGaN y de InAlN. Los resultados obtenidos en los transistores con barrera de AlGaN han presentado una disminución de la corriente de drenador y de la transconductancia sin mostrar un cambio en la tensión umbral. Por lo tanto, se puede deducir que la posible localización de las trampas es la región de acceso entre la puerta y el drenador. Por el contrario, la reducción de la corriente de drenador observada en los dispositivos con barrera de InAlN llevaba asociado un cambio significativo en la tensión umbral, lo que implica la existencia de trampas situadas en la zona debajo de la puerta. Además, el significativo aumento del valor de la resistencia-ON y la degradación de la transconductancia revelan la presencia de trampas en la zona de acceso entre la puerta y el drenador. La evaluación de los efectos del atrapamiento de carga en dispositivos con diferentes geometrías ha demostrado que dichos efectos son menos notables en aquellos transistores con mayor longitud de puerta o mayor distancia entre puerta y drenador. Esta dependencia con la geometría se puede explicar considerando que la longitud y densidad de trampas de la puerta virtual son independientes de las dimensiones del dispositivo. Finalmente se puede deducir que para conseguir el diseño óptimo durante la fase de diseño no sólo hay que tener en cuenta la aplicación final sino también la influencia que tiene la geometría en los diferentes aspectos estudiados (funcionamiento a alta temperatura, autocalentamiento, y atrapamiento de carga). ABSTRACT GaN-based high electron mobility transistors have been under extensive research due to the excellent electrical properties of GaN and its related alloys (high carrier concentration, high mobility, and high critical electric field). Although these devices have been recently included in commercial applications, some performance and reliability issues need to be addressed for their expansion in the market. Some of these relevant aspects have been studied during this thesis; for instance, the fabrication of enhancement mode HEMTs, the device performance at high temperature, the self-heating and the charge trapping. Enhancement mode HEMTs have become more attractive mainly because their use leads to a significant reduction of the power consumption during the stand-by state. Moreover, they enable the fabrication of simpler power amplifier circuits and high-power switches because they allow the elimination of negativepolarity voltage supply, reducing significantly the circuit complexity and system cost. In this thesis, different techniques for the fabrication of these devices have been assessed: wet-etching for achieving the gate-recess in InAl(Ga)N/GaN devices and two different fluorine-based treatments (CF4 plasma and F implantation). Regarding the wet-etching, experiments have been carried out in InAl(Ga)N/GaN grown on different substrates: Si, sapphire, and SiC. The total recess of the barrier was achieved after 3 min of etching in devices grown on Si substrate. This suggests that the etch rate can critically depend on the dislocations present in the structure, since the Si exhibits the highest mismatch to GaN. Concerning the fluorine-based treatments, a post-gate thermal annealing was required to recover the damages caused to the structure during the fluorine-treatments. The study of the threshold voltage as a function of this annealing time has revealed that in the case of the plasma-treated devices it become more negative with the time increase. On the contrary, the threshold voltage of implanted HEMTs showed a positive shift when the annealing time was increased, which is attributed to the deep F implantation profile. Plasma-treated HEMTs have exhibited better DC performance at room temperature than the implanted devices. Their study at high temperature has revealed that their performance decreases with temperature. The initial performance measured at room temperature was recovered after the thermal cycle regardless of the fluorine treatment; therefore, the thermal effects were reversible. Thermal issues related to the device performance at different temperature have been addressed. Firstly, AlGaN/GaN HEMTs grown on Si substrate with different cap layers: GaN, in situ SiN, or in situ SiN/GaN, have been assessed from 25 K to 550 K. In situ SiN cap layer has been demonstrated to improve the device performance since HEMTs with this cap layer have exhibited the highest drain current and transconductance values, the lowest on-resistance, as well as the best off-state characteristics. Moreover, the evaluation of thermal stress impact on the device performance has confirmed the robustness of devices with in situ cap. Secondly, the high temperature performance of InAlN/GaN HEMTs with different layouts and geometries have been assessed. The devices under study have exhibited an almost linear reduction of the main DC parameters operating in a temperature range from room temperature to 225°C. This was mainly due to the thermal dependence of the electron mobility, and secondly to the drift velocity decrease with temperature. Moreover, HEMTs with large gate length values have exhibited a great reduction of the device performance. This was attributed to the greater decrease of the drift velocity for low electric fields. Similarly, the increase of the gate-to-drain distance led to a greater reduction of drain current and transconductance values. Therefore, this thermal performance degradation has been found to be dependent on both the gate length and the gate-to-drain distance. It was observed that the very high power density in the active region of these transistors leads to Joule self-heating, resulting in an increase of the device temperature, which can degrade the device performance and reliability. A simple electrical method have been developed during this work to determine the channel temperature. Furthermore, the application of this technique together with the performance of electro-thermal simulations have enabled the evaluation of different aspects related to the self-heating. For instance, the influence of the substrate have been confirmed by the study of devices grown on Si, SiC, and Sapphire. HEMTs grown on SiC substrate have been confirmed to exhibit the lowest self-heating effects thanks to its highest thermal conductivity. In addition to this, the distribution of the generated heat in the channel has been demonstrated to be dependent on the gate-to-drain distance. Besides the substrate and the geometry of the device, the ambient temperature has also been found to be relevant for the self-heating effects, mainly due to the temperature-dependent thermal conductivity of the layers and the substrate. Trapping effects have been evaluated by means of pulsed measurements in AlGaN and InAIN barrier devices. AlGaN barrier HEMTs have exhibited a de crease in drain current and transconductance without measurable threshold voltage change, suggesting the location of the traps in the gate-to-drain access region. On the contrary, InAIN barrier devices have showed a drain current associated with a positive shift of threshold voltage, which indicated that the traps were possibly located under the gate region. Moreover, a significant increase of the ON-resistance as well as a transconductance reduction were observed, revealing the presence of traps on the gate-drain access region. On the other hand, the assessment of devices with different geometries have demonstrated that the trapping effects are more noticeable in devices with either short gate length or the gate-to-drain distance. This can be attributed to the fact that the length and the trap density of the virtual gate are independent on the device geometry. Finally, it can be deduced that besides the final application requirements, the influence of the device geometry on the performance at high temperature, on the self-heating, as well as on the trapping effects need to be taken into account during the device design stage to achieve the optimal layout.

Increased size selectivity of Si quantum dots on SiC at low substrate temperatures : an ion-assisted self-organization approach

A simple, effective, and innovative approach based on ion-assisted self-organization is proposed to synthesize size-selected Si quantum dots (QDs) on SiC substrates at low substrate temperatures. Using hybrid numerical simulations, the formation of Si QDs through a self-organization approach is investigated by taking into account two distinct cases of Si QD formation using the ionization energy approximation theory, which considers ionized in-fluxes containing Si3+ and Si1+ ions in the presence of a microscopic nonuniform electric field induced by a variable surface bias. The results show that the highest percentage of the surface coverage by 1 and 2 nm size-selected QDs was achieved using a bias of -20 V and ions in the lowest charge state, namely, Si1+ ions in a low substrate temperature range (227-327 °C). As low substrate temperatures (≤500 °C) are desirable from a technological point of view, because (i) low-temperature deposition techniques are compatible with current thin-film Si-based solar cell fabrication and (ii) high processing temperatures can frequently cause damage to other components in electronic devices and destroy the tandem structure of Si QD-based third-generation solar cells, our results are highly relevant to the development of the third-generation all-Si tandem photovoltaic solar cells.

Epitaxial SiC grown on silicon-on-insulator substrate with ultra-thin silicon-over-layer

We report on the comparative studies of epitaxial SiC films grown on silicon-on-insulator (SOI) and Si bulk substrates. The silicon-over-layer (SOL) on the SOI has been thinned down to different thicknesses, with the thinnest about 10 nm. It has been found that the full-width-at-half-maxim in the X-ray diffraction spectrum from the SiC films decreases as the SOL thickness decreases, indicating improved quality of the SiC film. A similar trend has also been found in the Raman spectrum. One of the potential explanations for the observation is strain accommodation by the ultra-thin SOI substrate. (c) 2005 Elsevier B.V. All rights reserved.

Strain accommodation of 3C-SiC grown on hydrogen-implanted Si (001) substrate

The hydrogen-implanted Si substrate has been used for the fabrication of the "compliant substrate", which can accommodate the mismatch strain during the heteroepitaxy. The compliance of the substrate can be modulated by the energy and dose of implanted hydrogen. In addition, the defects caused by implantation act as the gettering center for the internal gettering of the harmful metallic impurities. Compared with SiC films growth on substrate without implantation. all the measurements indicated that the mismatch strains in the SiC films grown on this substrate have been released and the crystalline qualities have been improved. It is a practical technique used for the compliant substrate fabrication and compatible with the semiconductor industry. (C) 2003 Elsevier B.V. All rights reserved.

Heteroepitaxial Growth of 3C-SiC on Si (111) Substrate using AlN as a Buffer Layer

Using AlN as a buffer layer, 3C-SiC film has been grown on Si substrate by low pressure chemical vapor deposition (LPCVD). Firstly growth of AlN thin films on Si substrates under varied V/III ratios at 1100 degrees was investigated and the (002) preferred orientational growth with good crystallinity was obtained at the V/III ratio of 10000. Annealing at 1300 degrees C indicated the surface morphology and crystallinity stability of AlN film. Secondly the 3C-SiC film was grown on Si substrate with AlN buffer layer. Compared to that without AlN buffer layer, the crystal quality of the 3C-SiC film was improved on the AlN/Si substrate, characterized by X-ray diffraction (XRD) and Raman measurements.

Effect of Silicon-on-Insulator Substrate on Residual Strain in 3C-SiC Films

One group of SiC films are grown on silicon-on-insulator （SOI） substrates with a series of silicon-overlayer thickness. Raman scattering spectroscopy measurement clearly indicates that a systematic trend of residual stress reduction as the silicon over-layer thickness decreases for the SOI substrates. Strain relaxation in the SiC epilayer is explained by force balance approach and near coincidence lattice model.

Phase composition, microstructure and microhardness of electroless nickel composite coating co-deposited with SiC on cast aluminium LM24 alloy substrate

Electroless Ni–P (EN) and composite Ni–P–SiC (ENC) coatings were developed on cast aluminium alloy substrate, LM24. The coating phase composition, microstructure and microhardness were investigated using X-ray diffraction (XRD), scanning electron microscopy (SEM) and microhardness tester, respectively, on as-plated and heat-treated specimens. The original microstructure of the Ni–P matrix is not affected by the inclusion of the hard particles SiC. No formation of Ni–Si phase was observed up to 500 °C of heat treatment. The microhardness is increased on incorporation of SiC in Ni–P matrix. The hardening mechanism is the formation of intermetallic phase Ni3P on annealing at elevated temperature.

Characterisation of phase composition, microstructure and microhardness of electroless nickel composite coating co-deposited with SiC on casting aluminium LM24 alloy substrate

Electroless Ni-P (EN) and composite Ni-P-SiC (ENC) coatings were developed on cast aluminium alloy, LM24. The coating phase composition, microstructure and microhardness were investigated using X-ray diffraction (XRD), scanning electron microscopy (SEM) and microhardness tester, respectively, on as-plated and heat-treated specimens. The original microstructure of the Ni-P matrix is not affected by the inclusion of the hard particles SiC. No formation of Ni-Si phase was observed upto 500°C of heat treatment. The microhardness is increased on incorporation of SiC in Ni-P matrix. The hardening mechanism is the formation of intermetallic phase Ni3P on annealing at elevated temperature. Overall, the composite coating (ENC) was found to be superior as compared to particles free (EN) coating in both as-deposited and heat-treated conditions.

Si quantum dots embedded in an amorphous SiC matrix : nanophase control by non-equilibrium plasma hydrogenation

Nanophase nc-Si/a-SiC films that contain Si quantum dots (QDs) embedded in an amorphous SiC matrix were deposited on single-crystal silicon substrates using inductively coupled plasma-assisted chemical vapor deposition from the reactive silane and methane precursor gases diluted with hydrogen at a substrate temperature of 200 °C. The effect of the hydrogen dilution ratio X (X is defined as the flow rate ratio of hydrogen-to-silane plus methane gases), ranging from 0 to 10.0, on the morphological, structural, and compositional properties of the deposited films, is extensively and systematically studied by scanning electron microscopy, high-resolution transmission electron microscopy, X-ray diffraction, Raman spectroscopy, Fourier-transform infrared absorption spectroscopy, and X-ray photoelectron spectroscopy. Effective nanophase segregation at a low hydrogen dilution ratio of 4.0 leads to the formation of highly uniform Si QDs embedded in the amorphous SiC matrix. It is also shown that with the increase of X, the crystallinity degree and the crystallite size increase while the carbon content and the growth rate decrease. The obtained experimental results are explained in terms of the effect of hydrogen dilution on the nucleation and growth processes of the Si QDs in the high-density plasmas. These results are highly relevant to the development of next-generation photovoltaic solar cells, light-emitting diodes, thin-film transistors, and other applications.

Single-step, rapid low-temperature synthesis of Si quantum dots embedded in an amorphous SiC matrix in high-density reactive plasmas

A simple, effective and innovative approach based on low-pressure, thermally nonequilibrium, high-density inductively coupled plasmas is proposed to rapidly synthesize Si quantum dots (QDs) embedded in an amorphous SiC (a-SiC) matrix at a low substrate temperature and without any commonly used hydrogen dilution. The experimental results clearly demonstrate that uniform crystalline Si QDs with a size of 3-4 nm embedded in the silicon-rich (carbon content up to 10.7at.%) a-SiC matrix can be formed from the reactive mixture of silane and methane gases, with high growth rates of ∼1.27-2.34 nm s-1 and at a low substrate temperature of 200 °C. The achievement of the high-rate growth of Si QDs embedded in the a-SiC without any commonly used hydrogen dilution is discussed based on the unique properties of the inductively coupled plasma-based process. This work is particularly important for the development of the all-Si tandem cell-based third generation photovoltaic solar cells.

Microstructure control and wear of Al2O3-SiC-(Al,Si) composites made by melt oxidation

Ceramic matrix composites of Al2O3-SiC-(Al,Si) have been fabricated by directed melt oxidation of aluminum alloys into SiC particulate preforms. The proportions of Al2O3, alloy, and porosity in the composite can be controlled by proper selection of SLC particle size and the processing temperature. The wear resistance of composites was evaluated in pin-on-disk experiments against a hard steel substrate. Minimum wear rate comparable to conventional ceramics such as ZTA is recorded for the composition containing the highest fraction of alloy, owing to the development of a thin and adherent tribofilm with a low coefficient of friction.