998 resultados para Architecture, Medieval
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Purpose – The purpose of this paper is to identify the main practitioners, goods, customers and locations of secondhand marketing activities in late medieval England. It questions how important was the economic role played by such markets and what was the interaction with more formal market structures?
Design/methodology/approach – A broad range of evidence was examined, covering the period from 1200 to 1500: regulations, court rolls, wills, manorial accounts, literature, and even archaeology. Such material often provided mere scraps of information about marginal marketing activity and it was important to recognise the severe limitations of the evidence. Nevertheless, a wide survey of the available sources can give us an insight into medieval attitudes towards such trade, as well as reminding us that much marketing activity occurred beyond the reach of the surviving documentation.
Findings – Late medieval England had numerous outlets for secondhand items, from sellers of used clothes and furs who wandered the marketplaces to craftsmen who recycled and mended old materials. Secondhand marketing was an important part of the medieval makeshift economy, serving not only the needs of the lower sectors of society but also those aspiring to a higher status. However, it is unlikely that such trade generated much profit and the traders were often viewed as marginal, suspicious and even fraudulent.
Originality/value – There is a distinct lack of research into the extent of and significance of medieval secondhand marketing, which existed in the shadowy margins of formal markets and is thus poorly represented in the primary sources. A broad-based approach to the evidence can highlight a variety of important issues, which impact upon the understanding of the medieval English economy.
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The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s. © 2006 IEEE.
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Two poems
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A key issue in the design of next generation Internet routers and switches will be provision of traffic manager (TM) functionality in the datapaths of their high speed switching fabrics. A new architecture that allows dynamic deployment of different TM functions is presented. By considering the processing requirements of operations such as policing and congestion, queuing, shaping and scheduling, a solution has been derived that is scalable with a consistent programmable interface. Programmability is achieved using a function computation unit which determines the action (e.g. drop, queue, remark, forward) based on the packet attribute information and a memory storage part. Results of a Xilinx Virtex-5 FPGA reference design are presented.
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A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.