Models and methods for power monolithic microwave integrated circuits

Computer aided design of Monolithic Microwave Integrated Circuits (MMICs) depends critically on active device models that are accurate, computationally efficient, and easily extracted from measurements or device simulators. Empirical models of active electron devices, which are based on actual device measurements, do not provide a detailed description of the electron device physics. However they are numerically efficient and quite accurate. These characteristics make them very suitable for MMIC design in the framework of commercially available CAD tools. In the empirical model formulation it is very important to separate linear memory effects (parasitic effects) from the nonlinear effects (intrinsic effects). Thus an empirical active device model is generally described by an extrinsic linear part which accounts for the parasitic passive structures connecting the nonlinear intrinsic electron device to the external world. An important task circuit designers deal with is evaluating the ultimate potential of a device for specific applications. In fact once the technology has been selected, the designer would choose the best device for the particular application and the best device for the different blocks composing the overall MMIC. Thus in order to accurately reproducing the behaviour of different-in-size devices, good scalability properties of the model are necessarily required. Another important aspect of empirical modelling of electron devices is the mathematical (or equivalent circuit) description of the nonlinearities inherently associated with the intrinsic device. Once the model has been defined, the proper measurements for the characterization of the device are performed in order to identify the model. Hence, the correct measurement of the device nonlinear characteristics (in the device characterization phase) and their reconstruction (in the identification or even simulation phase) are two of the more important aspects of empirical modelling. This thesis presents an original contribution to nonlinear electron device empirical modelling treating the issues of model scalability and reconstruction of the device nonlinear characteristics. The scalability of an empirical model strictly depends on the scalability of the linear extrinsic parasitic network, which should possibly maintain the link between technological process parameters and the corresponding device electrical response. Since lumped parasitic networks, together with simple linear scaling rules, cannot provide accurate scalable models, either complicate technology-dependent scaling rules or computationally inefficient distributed models are available in literature. This thesis shows how the above mentioned problems can be avoided through the use of commercially available electromagnetic (EM) simulators. They enable the actual device geometry and material stratification, as well as losses in the dielectrics and electrodes, to be taken into account for any given device structure and size, providing an accurate description of the parasitic effects which occur in the device passive structure. It is shown how the electron device behaviour can be described as an equivalent two-port intrinsic nonlinear block connected to a linear distributed four-port passive parasitic network, which is identified by means of the EM simulation of the device layout, allowing for better frequency extrapolation and scalability properties than conventional empirical models. Concerning the issue of the reconstruction of the nonlinear electron device characteristics, a data approximation algorithm has been developed for the exploitation in the framework of empirical table look-up nonlinear models. Such an approach is based on the strong analogy between timedomain signal reconstruction from a set of samples and the continuous approximation of device nonlinear characteristics on the basis of a finite grid of measurements. According to this criterion, nonlinear empirical device modelling can be carried out by using, in the sampled voltage domain, typical methods of the time-domain sampling theory.

Analisi e razionalizzazione dei flussi di materiale in ingresso e dei trasporti in un'ottica di logistica integrata: il caso Denso Manufacturing Italia S.p.A.

Negli ultimi anni è emerso chiaramente come la logistica rivesta un’importanza fondamentale per le aziende e costituisca un ottimo strumento per assicurarsi e mantenere un solido vantaggio competitivo. Inoltre, osservando l’ambiente attuale si evince come il sistema logistico sia caratterizzato da un progressivo aumento di complessità, sia in seguito alle maggiori esigenze dei mercati e sia come conseguenza della globalizzazione. In questo quadro evolutivo è mutato profondamente il ruolo ricoperto dalla logistica all’interno delle organizzazioni. Rispetto alla concezione tradizionale, che considerava la logistica come una funzione esclusivamente interna all’azienda, si è assistito al progressivo coinvolgimento dei fornitori e dei clienti ed è emersa la necessità di coordinare gli sforzi dell’intera supply chain, con l’obiettivo di migliorare il livello di servizio globalmente offerto e di ridurre i costi logistici totali. Tali considerazioni sono state il filo conduttore dell’analisi presentata di seguito, basata su uno studio svolto presso la DENSO Manufacturing Italia S.p.A., finalizzato all’analisi dei flussi in ingresso ed in particolar modo alla razionalizzazione degli imballi e dei trasporti, in un’ottica di integrazione con i fornitori. In particolare, la prima parte della trattazione introduce gli argomenti dal punto di vista teorico. Infatti, nel primo capitolo verrà illustrato il tema della logistica integrata e della sua evoluzione nel tempo, in relazione all’ambiente competitivo attuale ed alle nuove richieste dei mercati, approfondendo il tema della logistica in ingresso e del trasporto merci. Quindi, nel secondo capitolo verrà trattato il tema degli imballi, analizzandone le ripercussioni sull’intera catena logistica ed offrendo una panoramica dei metodi che permettono l’integrazione tra gli imballaggi ed i sistemi di trasporto, movimentazione e stoccaggio. Invece, la seconda parte dello studio sarà dedicata alla presentazione dell’azienda in cui è stato realizzato il progetto di tesi. Nel terzo capitolo verranno introdotte sia la multinazionale giapponese DENSO Corporation che la sua consociata DENSO Manufacturing Italia S.p.A., specializzata nella produzione di componenti per il mercato automotive, presso cui si è svolto lo studio. Nel quarto capitolo verrà descritto il layout dell’impianto, per poi presentare la logistica in ingresso allo stabilimento, ponendo maggiore attenzione ai flussi provenienti dal nord Italia – ed in particolare dal Piemonte – su cui si incentra il lavoro di tesi. Quindi, nella terza ed ultima parte verrà presentata in dettaglio l’analisi condotta durante lo studio aziendale. In particolare, il quinto capitolo tratta dei flussi di materiale provenienti dall’area piemontese, con l’analisi degli imballi utilizzati dai fornitori, delle consegne e delle modalità di trasporto. Infine, nel sesto capitolo saranno proposte delle soluzioni migliorative relativamente a tutte le criticità emerse in fase di analisi, valutandone gli impatti sia in termini economici che in relazione all’efficienza del flusso logistico.

Tecniche di progettazione tollerante alle variazioni per circuiti digitali in tecnologie nanometriche

The digital electronic market development is founded on the continuous reduction of the transistors size, to reduce area, power, cost and increase the computational performance of integrated circuits. This trend, known as technology scaling, is approaching the nanometer size. The lithographic process in the manufacturing stage is increasing its uncertainty with the scaling down of the transistors size, resulting in a larger parameter variation in future technology generations. Furthermore, the exponential relationship between the leakage current and the threshold voltage, is limiting the threshold and supply voltages scaling, increasing the power density and creating local thermal issues, such as hot spots, thermal runaway and thermal cycles. In addiction, the introduction of new materials and the smaller devices dimension are reducing transistors robustness, that combined with high temperature and frequently thermal cycles, are speeding up wear out processes. Those effects are no longer addressable only at the process level. Consequently the deep sub-micron devices will require solutions which will imply several design levels, as system and logic, and new approaches called Design For Manufacturability (DFM) and Design For Reliability. The purpose of the above approaches is to bring in the early design stages the awareness of the device reliability and manufacturability, in order to introduce logic and system able to cope with the yield and reliability loss. The ITRS roadmap suggests the following research steps to integrate the design for manufacturability and reliability in the standard CAD automated design flow: i) The implementation of new analysis algorithms able to predict the system thermal behavior with the impact to the power and speed performances. ii) High level wear out models able to predict the mean time to failure of the system (MTTF). iii) Statistical performance analysis able to predict the impact of the process variation, both random and systematic. The new analysis tools have to be developed beside new logic and system strategies to cope with the future challenges, as for instance: i) Thermal management strategy that increase the reliability and life time of the devices acting to some tunable parameter,such as supply voltage or body bias. ii) Error detection logic able to interact with compensation techniques as Adaptive Supply Voltage ASV, Adaptive Body Bias ABB and error recovering, in order to increase yield and reliability. iii) architectures that are fundamentally resistant to variability, including locally asynchronous designs, redundancy, and error correcting signal encodings (ECC). The literature already features works addressing the prediction of the MTTF, papers focusing on thermal management in the general purpose chip, and publications on statistical performance analysis. In my Phd research activity, I investigated the need for thermal management in future embedded low-power Network On Chip (NoC) devices.I developed a thermal analysis library, that has been integrated in a NoC cycle accurate simulator and in a FPGA based NoC simulator. The results have shown that an accurate layout distribution can avoid the onset of hot-spot in a NoC chip. Furthermore the application of thermal management can reduce temperature and number of thermal cycles, increasing the systemreliability. Therefore the thesis advocates the need to integrate a thermal analysis in the first design stages for embedded NoC design. Later on, I focused my research in the development of statistical process variation analysis tool that is able to address both random and systematic variations. The tool was used to analyze the impact of self-timed asynchronous logic stages in an embedded microprocessor. As results we confirmed the capability of self-timed logic to increase the manufacturability and reliability. Furthermore we used the tool to investigate the suitability of low-swing techniques in the NoC system communication under process variations. In this case We discovered the superior robustness to systematic process variation of low-swing links, which shows a good response to compensation technique as ASV and ABB. Hence low-swing is a good alternative to the standard CMOS communication for power, speed, reliability and manufacturability. In summary my work proves the advantage of integrating a statistical process variation analysis tool in the first stages of the design flow.

Enabling Blocks for Integrated CMOS UWB Transceivers

The last decades have seen an unrivaled growth and diffusion of mobile telecommunications. Several standards have been developed to this purposes, from GSM mobile phone communications to WLAN IEEE 802.11, providing different services for the the transmission of signals ranging from voice to high data rate digital communications and Digital Video Broadcasting (DVB). In this wide research and market field, this thesis focuses on Ultra Wideband (UWB) communications, an emerging technology for providing very high data rate transmissions over very short distances. In particular the presented research deals with the circuit design of enabling blocks for MB-OFDM UWB CMOS single-chip transceivers, namely the frequency synthesizer and the transmission mixer and power amplifier. First we discuss three different models for the simulation of chargepump phase-locked loops, namely the continuous time s-domain and discrete time z-domain approximations and the exact semi-analytical time-domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling time as a function of loop parameters, deriving practical conditions under which the different models are reliable for fast settling PLLs up to fourth order. Besides, a phase noise analysis method based upon the time-domain model is introduced and compared to the results obtained by means of the s-domain model. We compare the three models over the simulation of a fast switching PLL to be integrated in a frequency synthesizer for WiMedia MB-OFDM UWB systems. In the second part, the theoretical analysis is applied to the design of a 60mW 3.4 to 9.2GHz 12 Bands frequency synthesizer for MB-OFDM UWB based on two wide-band PLLs. The design is presented and discussed up to layout level. A test chip has been implemented in TSMC CMOS 90nm technology, measured data is provided. The functionality of the circuit is proved and specifications are met with state-of-the-art area occupation and power consumption. The last part of the thesis deals with the design of a transmission mixer and a power amplifier for MB-OFDM UWB band group 1. The design has been carried on up to layout level in ST Microlectronics 65nm CMOS technology. Main characteristics of the systems are the wideband behavior (1.6 GHz of bandwidth) and the constant behavior over process parameters, temperature and supply voltage thanks to the design of dedicated adaptive biasing circuits.

Neutronics analyses for fast spectrum nuclear systems and scenario studies for advanced nuclear fuel cycles

The present PhD thesis summarizes the three-years study about the neutronic investigation of a new concept nuclear reactor aiming at the optimization and the sustainable management of nuclear fuel in a possible European scenario. A new generation nuclear reactor for the nuclear reinassance is indeed desired by the actual industrialized world, both for the solution of the energetic question arising from the continuously growing energy demand together with the corresponding reduction of oil availability, and the environment question for a sustainable energy source free from Long Lived Radioisotopes and therefore geological repositories. Among the Generation IV candidate typologies, the Lead Fast Reactor concept has been pursued, being the one top rated in sustainability. The European Lead-cooled SYstem (ELSY) has been at first investigated. The neutronic analysis of the ELSY core has been performed via deterministic analysis by means of the ERANOS code, in order to retrieve a stable configuration for the overall design of the reactor. Further analyses have been carried out by means of the Monte Carlo general purpose transport code MCNP, in order to check the former one and to define an exact model of the system. An innovative system of absorbers has been conceptualized and designed for both the reactivity compensation and regulation of the core due to cycle swing, as well as for safety in order to guarantee the cold shutdown of the system in case of accident. Aiming at the sustainability of nuclear energy, the steady-state nuclear equilibrium has been investigated and generalized into the definition of the ``extended'' equilibrium state. According to this, the Adiabatic Reactor Theory has been developed, together with a New Paradigm for Nuclear Power: in order to design a reactor that does not exchange with the environment anything valuable (thus the term ``adiabatic''), in the sense of both Plutonium and Minor Actinides, it is required indeed to revert the logical design scheme of nuclear cores, starting from the definition of the equilibrium composition of the fuel and submitting to the latter the whole core design. The New Paradigm has been applied then to the core design of an Adiabatic Lead Fast Reactor complying with the ELSY overall system layout. A complete core characterization has been done in order to asses criticality and power flattening; a preliminary evaluation of the main safety parameters has been also done to verify the viability of the system. Burn up calculations have been then performed in order to investigate the operating cycle for the Adiabatic Lead Fast Reactor; the fuel performances have been therefore extracted and inserted in a more general analysis for an European scenario. The present nuclear reactors fleet has been modeled and its evolution simulated by means of the COSI code in order to investigate the materials fluxes to be managed in the European region. Different plausible scenarios have been identified to forecast the evolution of the European nuclear energy production, including the one involving the introduction of Adiabatic Lead Fast Reactors, and compared to better analyze the advantages introduced by the adoption of new concept reactors. At last, since both ELSY and the ALFR represent new concept systems based upon innovative solutions, the neutronic design of a demonstrator reactor has been carried out: such a system is intended to prove the viability of technology to be implemented in the First-of-a-Kind industrial power plant, with the aim at attesting the general strategy to use, to the largest extent. It was chosen then to base the DEMO design upon a compromise between demonstration of developed technology and testing of emerging technology in order to significantly subserve the purpose of reducing uncertainties about construction and licensing, both validating ELSY/ALFR main features and performances, and to qualify numerical codes and tools.

Algorithms and Models For Combinatorial Optimization Problems

In this thesis we present some combinatorial optimization problems, suggest models and algorithms for their effective solution. For each problem,we give its description, followed by a short literature review, provide methods to solve it and, finally, present computational results and comparisons with previous works to show the effectiveness of the proposed approaches. The considered problems are: the Generalized Traveling Salesman Problem (GTSP), the Bin Packing Problem with Conflicts(BPPC) and the Fair Layout Problem (FLOP).

Progettazione del riduttore in un sistema di trasmissione per autoveicoli a propulsione ibrida completa

Questa tesi di laurea descrive il progetto del riduttore, usato per realizzare la trasmissione del moto dal motore elettrico alle ruote di un autoveicolo ibrido o elettrico. Per prima cosa vengono analizzate le caratteristiche richieste al riduttore, definendone il layout ed il rapporto di riduzione; successivamente si studiano le sollecitazioni a cui il rotismo sarà sottoposto, per definire correttamente un ciclo di carico da usare nel dimensionamento dei vari componenti. Fatto ciò, vengono calcolati e modellati i componenti interni del riduttore. Infine viene anche eseguito uno studio funzionale della carcassa che dovrà contenere tali componenti.

Electrothermal characterization and nonlinear modelling of GaN transistors for telecommunication circuit design

This thesis starts showing the main characteristics and application fields of the AlGaN/GaN HEMT technology, focusing on reliability aspects essentially due to the presence of low frequency dispersive phenomena which limit in several ways the microwave performance of this kind of devices. Based on an equivalent voltage approach, a new low frequency device model is presented where the dynamic nonlinearity of the trapping effect is taken into account for the first time allowing considerable improvements in the prediction of very important quantities for the design of power amplifier such as power added efficiency, dissipated power and internal device temperature. An innovative and low-cost measurement setup for the characterization of the device under low-frequency large-amplitude sinusoidal excitation is also presented. This setup allows the identification of the new low frequency model through suitable procedures explained in detail. In this thesis a new non-invasive empirical method for compact electrothermal modeling and thermal resistance extraction is also described. The new contribution of the proposed approach concerns the non linear dependence of the channel temperature on the dissipated power. This is very important for GaN devices since they are capable of operating at relatively high temperatures with high power densities and the dependence of the thermal resistance on the temperature is quite relevant. Finally a novel method for the device thermal simulation is investigated: based on the analytical solution of the tree-dimensional heat equation, a Visual Basic program has been developed to estimate, in real time, the temperature distribution on the hottest surface of planar multilayer structures. The developed solver is particularly useful for peak temperature estimation at the design stage when critical decisions about circuit design and packaging have to be made. It facilitates the layout optimization and reliability improvement, allowing the correct choice of the device geometry and configuration to achieve the best possible thermal performance.

Progetto e realizzazione di riferimenti in tensione simmetrici in tecnologia CMOS

La tesi tratta del progetto e della realizzazione di un riferimento in tensione simmetrico e stabile in temperatura, realizzato in tecnologia CMOS. Nella progettazione analogica ad alta precisione ha assunto sempre più importanza il problema della realizzazione di riferimenti in tensione stabili in temperatura. Nella maggior parte dei casi vengono presentati Bandgap, ovvero riferimenti in tensione che sfruttano l'andamento in temperatura dell'energy gap del silicio al fine di ottenere una tensione costante in un ampio range di temperatura. Tale architettura risulta utile nei sistemi ad alimentazione singola compresa fra 0 e Vdd essendo in grado di generare una singola tensione di riferimento del valore tipico di 1.2V. Nella tesi viene presentato un riferimento in tensione in grado di offrire le stesse prestazioni di un Bandgap per quanto riguarda la variazione in temperatura ma in grado di lavorare sia in sistemi ad alimentazione singola che ad alimentazione duale. Il circuito proposto e' in grado di generare due tensioni, simmetriche rispetto a un riferimento dato, del valore nominale di ±450mV. All'interno della tesi viene descritto il progetto di due diverse architetture, entrambe in grado di generare le tensioni con le specifiche richieste. Le due architetture sono poi state confrontate analizzando in particolare la stabilità in temperatura, la potenza dissipata, il PSRR (Power Supply Rejection Ratio) e la simmetria delle tensioni generate. Al termine dell'analisi è stato poi implementato su silicio il circuito che garantiva le prestazioni migliori. In sede di disegno del layout su silicio sono stati affrontati i problemi derivanti dall'adattamento dei componenti al fine di ottenere una maggiore insensibilità del circuito stesso alle incertezze legate al processo di realizzazione. Infine sono state effettuate le misurazioni attraverso una probe station a 4 sonde per verificare il corretto funzionamento del circuito e le sue prestazioni.

Progettazione e sviluppo di estensioni per AContent

In questo documento di tesi viene descritta la progettazione e la realizzazione di estensioni per il sistema di authoring AContent. L'idea è di creare un'estensione dell'authoring tool che implementi il concetto di template ovvero strumenti di grande efficacia e di facile utilizzo nelle fasi di redazione dei contenuti. Si prevede di aggiungerli ad AContent senza la necessità di integrare un intero motore di template ma utilizzando strutture dati esistenti e specifiche standard di e-learning. I servizi aggiuntivi da offrire agli autori sono stati organizzati secondo tre approcci diversi da cui sono emersi tre livelli di template. Il Template di Layout che determina l'aspetto grafico dei contenuti, il Template di Pagina che definisce la struttura di ogni singola pagina e il Template di Struttura che propone e imposta un modello per la struttura dell'intero contenuto didattico. Il documento è costituito da una seconda parte di progetto che va a coinvolgere il sistema ATutor e pone grande attenzione sulle caratteristiche di interoperabilità fra l'authoring AContent e il LCMS ATutor. Lo scopo è quello di estendere le funzionalità di integrazione dei contenuti del sistema così da presentare materiale didattico esterno archiviato in AContent. Viene trattata l'integrazione di LTI all'interno dei due sistemi considerati assegnando i ruoli di Tool Provider (AContent), fornitore di contenuti didattici remoti e Tool Consumer (ATutor), richiedente di tali contenuti. Sono considerati, infine, i due moduli di ATutor AContent Repository e External Tool che si occupano di importare materiale didattico da AContent tramite il Web Service REST. Si prevede la loro modifica affinché, attraverso il canale di comunicazione LTI stabilito, siano in grado di creare dei Live Content Link ovvero riferimenti a contenuti remoti (esterni alla piattaforma utilizzata) aggiornati in tempo reale. Infatti, a differenza di una normale importazione di un LO esterno è previsto che venga creano un "riferimento". In questo modo, la modifica di una pagina sul Tool Provider AContent si ripercuoterà istantaneamente su tutti i contenuti dei Tool Consumer che hanno instaurato un Live Content Link con il provider.

Cache-aware development of high integrity real-time systems

Cost, performance and availability considerations are forcing even the most conservative high-integrity embedded real-time systems industry to migrate from simple hardware processors to ones equipped with caches and other acceleration features. This migration disrupts the practices and solutions that industry had developed and consolidated over the years to perform timing analysis. Industry that are confident with the efficiency/effectiveness of their verification and validation processes for old-generation processors, do not have sufficient insight on the effects of the migration to cache-equipped processors. Caches are perceived as an additional source of complexity, which has potential for shattering the guarantees of cost- and schedule-constrained qualification of their systems. The current industrial approach to timing analysis is ill-equipped to cope with the variability incurred by caches. Conversely, the application of advanced WCET analysis techniques on real-world industrial software, developed without analysability in mind, is hardly feasible. We propose a development approach aimed at minimising the cache jitters, as well as at enabling the application of advanced WCET analysis techniques to industrial systems. Our approach builds on:(i) identification of those software constructs that may impede or complicate timing analysis in industrial-scale systems; (ii) elaboration of practical means, under the model-driven engineering (MDE) paradigm, to enforce the automated generation of software that is analyzable by construction; (iii) implementation of a layout optimisation method to remove cache jitters stemming from the software layout in memory, with the intent of facilitating incremental software development, which is of high strategic interest to industry. The integration of those constituents in a structured approach to timing analysis achieves two interesting properties: the resulting software is analysable from the earliest releases onwards - as opposed to becoming so only when the system is final - and more easily amenable to advanced timing analysis by construction, regardless of the system scale and complexity.