805 resultados para secondary circuits
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O nome de Claude Elwood Shannon não é totalmente estranho aos pesquisadores de Comunicação Social. No entanto, parte de sua importância para a história da comunicação no século XX é pouco conhecida. Sua dissertação de mestrado e o artigo dela derivado (A Symbolic Analysis of Relay and Switching Circuits) foram essenciais para que o computador se tornasse uma máquina de comunicação e, conseqüentemente, penetrasse em nossa sociedade na forma como ocorre hoje. Este artigo revisa o primeiro grande trabalho de Shannon e explicita sua participação no contexto atual da comunicação.
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The recent advances in CMOS technology have allowed for the fabrication of transistors with submicronic dimensions, making possible the integration of tens of millions devices in a single chip that can be used to build very complex electronic systems. Such increase in complexity of designs has originated a need for more efficient verification tools that could incorporate more appropriate physical and computational models. Timing verification targets at determining whether the timing constraints imposed to the design may be satisfied or not. It can be performed by using circuit simulation or by timing analysis. Although simulation tends to furnish the most accurate estimates, it presents the drawback of being stimuli dependent. Hence, in order to ensure that the critical situation is taken into account, one must exercise all possible input patterns. Obviously, this is not possible to accomplish due to the high complexity of current designs. To circumvent this problem, designers must rely on timing analysis. Timing analysis is an input-independent verification approach that models each combinational block of a circuit as a direct acyclic graph, which is used to estimate the critical delay. First timing analysis tools used only the circuit topology information to estimate circuit delay, thus being referred to as topological timing analyzers. However, such method may result in too pessimistic delay estimates, since the longest paths in the graph may not be able to propagate a transition, that is, may be false. Functional timing analysis, in turn, considers not only circuit topology, but also the temporal and functional relations between circuit elements. Functional timing analysis tools may differ by three aspects: the set of sensitization conditions necessary to declare a path as sensitizable (i.e., the so-called path sensitization criterion), the number of paths simultaneously handled and the method used to determine whether sensitization conditions are satisfiable or not. Currently, the two most efficient approaches test the sensitizability of entire sets of paths at a time: one is based on automatic test pattern generation (ATPG) techniques and the other translates the timing analysis problem into a satisfiability (SAT) problem. Although timing analysis has been exhaustively studied in the last fifteen years, some specific topics have not received the required attention yet. One such topic is the applicability of functional timing analysis to circuits containing complex gates. This is the basic concern of this thesis. In addition, and as a necessary step to settle the scenario, a detailed and systematic study on functional timing analysis is also presented.
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The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.
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The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.
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With the ever increasing demands for high complexity consumer electronic products, market pressures demand faster product development and lower cost. SoCbased design can provide the required design flexibility and speed by allowing the use of IP cores. However, testing costs in the SoC environment can reach a substantial percent of the total production cost. Analog testing costs may dominate the total test cost, as testing of analog circuits usually require functional verification of the circuit and special testing procedures. For RF analog circuits commonly used in wireless applications, testing is further complicated because of the high frequencies involved. In summary, reducing analog test cost is of major importance in the electronic industry today. BIST techniques for analog circuits, though potentially able to solve the analog test cost problem, have some limitations. Some techniques are circuit dependent, requiring reconfiguration of the circuit being tested, and are generally not usable in RF circuits. In the SoC environment, as processing and memory resources are available, they could be used in the test. However, the overhead for adding additional AD and DA converters may be too costly for most systems, and analog routing of signals may not be feasible and may introduce signal distortion. In this work a simple and low cost digitizer is used instead of an ADC in order to enable analog testing strategies to be implemented in a SoC environment. Thanks to the low analog area overhead of the converter, multiple analog test points can be observed and specific analog test strategies can be enabled. As the digitizer is always connected to the analog test point, it is not necessary to include muxes and switches that would degrade the signal path. For RF analog circuits, this is specially useful, as the circuit impedance is fixed and the influence of the digitizer can be accounted for in the design phase. Thanks to the simplicity of the converter, it is able to reach higher frequencies, and enables the implementation of low cost RF test strategies. The digitizer has been applied successfully in the testing of both low frequency and RF analog circuits. Also, as testing is based on frequency-domain characteristics, nonlinear characteristics like intermodulation products can also be evaluated. Specifically, practical results were obtained for prototyped base band filters and a 100MHz mixer. The application of the converter for noise figure evaluation was also addressed, and experimental results for low frequency amplifiers using conventional opamps were obtained. The proposed method is able to enhance the testability of current mixed-signal designs, being suitable for the SoC environment used in many industrial products nowadays.
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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
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As florestas secundárias e plantações de espécies exóticas estão se expandindo nas paisagens tropicais. No entanto, nossa compreensão sobre o valor destas florestas para a conservação da biodiversidade de invertebrados ainda é incipiente. Neste trabalho, usamos a fauna de formigas de serapilheira para avaliar a diversidade desses insetos entre três florestas de Eucalyptus, sendo uma comercial (quatro anos de idade) e duas abandonadas em diferentes idades de regeneração (16 e 31 anos) e uma área de Mata Atlântica secundária. A riqueza total foi mais alta na floresta secundária e nos plantios de Eucalyptus abandonados há mais tempo. A densidade de espécies na floresta secundária foi significativamente maior quando comparado as plantações de Eucalyptus, mas não difere entre eucaliptais; análise de ordenação revelou diferenças na composição de espécies entre as plantações de Eucalyptus com subbosque ausente e com subbosque desenvolvido ou em desenvolvimento. Ainda, foi constatada uma sobreposição acentuada entre amostras de serapilheira das florestas de eucaliptos abandonadas há mais tempo e a floresta secundária. em geral, plantações de eucalipto foram caracterizadas pela presença de espécies generalistas e de ampla distribuição. Nossos resultados indicam que embora o subbosque de plantações de eucaliptos com maior idade de regeneração suporte um conjunto relativamente alto de espécies generalistas de formigas, é improvável que eucaliptais conservem a maioria das espécies de florestas primárias, especialmente predadores especializados, Dacetini e espécies nômades.
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Soil CO2 emission (FCO2) is governed by the inherent properties of the soil, such as bulk density (BD). Mapping of FCO2 allows the evaluation and identification of areas with different accumulation potential of carbon. However, FCO2 mapping over larger areas is not feasible due to the period required for evaluation. This study aimed to assess the quality of FCO2 spatial estimates using values of BD as secondary information. FCO2 and BD were evaluated on a regular sampling grid of 60 m × 60 m comprising 141 points, which was established on a sugarcane area. Four scenarios were defined according to the proportion of the number of sampling points of FCO2 to those of BD. For these scenarios, 67 (F67), 87 (F87), 107 (F107) and 127 (F127) FCO2 sampling points were used in addition to 127 BD sampling points used as supplementary information. The use of additional information from the BD provided an increase in the accuracy of the estimates only in the F107, F67 and F87 scenarios, respectively. The F87 scenario, with the approximate ratio between the FCO2 and BD of 1.00:1.50, presented the best relative improvement in the quality of estimates, thereby indicating that the BD should be sampled at a density 1.5 time greater than that applied for the FCO2. This procedure avoided problems related to the high temporal variability associated with FCO2, which enabled the mapping of this variable to be elaborated in large areas.
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Uma cadela de sete anos de idade foi trazida ao hospital veterinário Governador Laudo Natel pois apresentava estrangúria há dois meses. Os sinais clínicos desenvolveram-se dois dias após ovário-histerectomia de eleição. Exames radiográficos e ultrasonográficos sugeriram piometra de coto ou granuloma cervical e fistula vesicovaginal. Duas laparotomias foram realizadas para desfazer as adesões, mas não houve melhora nos sinais clínicos observados. Iniciou-se tratamento médico e oito meses depois o animal, novamente avaliado, apresentava-se sadio porém ainda com sinais de estrangúria.
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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
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Cells of Mikania glomerata, Cephaelis ipecacuanha and Maytenus aquifolia were co-cultured in a two-phase system using filter paper as a solid support. The species were co-cultured in all possible paired combinations. Interaction between Mikania and Maytenus cells resulted in increased biomass production of Maytenus cells, but the friedelin content was reduced. Co-cultivation of Cephaelis and Mikania cells enhanced coumarin content, but inhibited the growth of Mikania cells. However, yield of emetine as well as Cephaelis biomass accumulation were positively stimulated by the co-cultivation. Results indicate a possible occurrence of allelopathy in such a system.
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As all herbicides act on pathways or processes crucial to plants, in an inhibitory or stimulatory way, low doses of any herbicide might be used to beneficially modulate plant growth, development, or composition. Glyphosate, the most used herbicide in the world, is widely applied at low rates to ripen sugarcane. Low rates of glyphosate also can stimulate plant growth (this effect is called hormesis). When applied at recommended rates for weed control, glyphosate can inhibit rust diseases in glyphosate-resistant wheat and soybean. Fluridone blocks carotenoid biosynthesis by inhibition of phytoene desaturase and is effective in reducing the production of abscisic acid in drought-stressed plants. Among the acetolactate synthase inhibitors, sulfometuron-methyl is widely used to ripen sugarcane and imidazolinones can be used to suppress turf species growth. The application of protoporphyrinogen oxidase inhibitors can trigger plant defenses against pathogens. Glufosinate, a glutamine syntherase inhibitor, is also known to improve the control of plant diseases. Auxin agonists (i.e., dicamba and 2,4-D) are effective, low-cost plant growth regulators. Currently, auxin agonists are still used in tissue cultures to induce somatic embryogenesis and to control fruit ripening, to reduce drop of fruits, to enlarge fruit size, or to extend the harvest period in citrus orchards. At low doses, triazine herbicides stimulate growth through beneficial effects on nitrogen metabolism and through auxin-like effects. Thus, sublethal doses of several herbicides have applications other than weed control.
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Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)