Kv1.5 is a major component underlying the A-type potassium current in retinal arteriolar smooth muscle.

Little is known about the molecular characteristics of the voltage-activated K(+) (K(v)) channels that underlie the A-type K(+) current in vascular smooth muscle cells of the systemic circulation. We investigated the molecular identity of the A-type K(+) current in retinal arteriolar myocytes using patch-clamp techniques, RT-PCR, immunohistochemistry, and neutralizing antibody studies. The A-type K(+) current was resistant to the actions of specific inhibitors for K(v)3 and K(v)4 channels but was blocked by the K(v)1 antagonist correolide. No effects were observed with pharmacological agents against K(v)1.1/2/3/6 and 7 channels, but the current was partially blocked by riluzole, a K(v)1.4 and K(v)1.5 inhibitor. The current was not altered by the removal of extracellular K(+) but was abolished by flecainide, indicative of K(v)1.5 rather than K(v)1.4 channels. Transcripts encoding K(v)1.5 and not K(v)1.4 were identified in freshly isolated retinal arterioles. Immunofluorescence labeling confirmed a lack of K(v)1.4 expression and revealed K(v)1.5 to be localized to the plasma membrane of the arteriolar smooth muscle cells. Anti-K(v)1.5 antibody applied intracellularly inhibited the A-type K(+) current, whereas anti-K(v)1.4 antibody had no effect. Co-expression of K(v)1.5 with K(v)beta1 or K(v)beta3 accessory subunits is known to transform K(v)1.5 currents from delayed rectifers into A-type currents. K(v)beta1 mRNA expression was detected in retinal arterioles, but K(v)beta3 was not observed. K(v)beta1 immunofluorescence was detected on the plasma membrane of retinal arteriolar myocytes. The findings of this study suggest that K(v)1.5, most likely co-assembled with K(v)beta1 subunits, comprises a major component underlying the A-type K(+) current in retinal arteriolar smooth muscle cells

Inelastic current-voltage spectroscopy of atomic wires

A tight-binding model is developed to describe the electron-phonon coupling in atomic wires under an applied voltage and to model, their inelastic current-voltage spectroscopy. Particular longitudinal phonons are found to have greatly enhanced coupling to the electronic states of the system. This leads to a large drop in differential conductance at threshold energies associated with these phonons. It is found that with increasing tension these energies decrease, while the size of the conductance drops increases, in agreement with experiment.

Feasibility of online collaborative voltage stability control of power systems

This paper presents the results of feasibility study of a novel concept of power system on-line collaborative voltage stability control. The proposal of the on-line collaboration between power system controllers is to enhance their overall performance and efficiency to cope with the increasing operational uncertainty of modern power systems. In the paper, the framework of proposed on-line collaborative voltage stability control is firstly presented, which is based on the deployment of multi-agent systems and real-time communication for on-line collaborative control. Then two of the most important issues in implementing the proposed on-line collaborative voltage stability control are addressed: (1) Error-tolerant communication protocol for fast information exchange among multiple intelligent agents; (2) Deployment of multi-agent systems by using graph theory to implement power system post-emergency control. In the paper, the proposed on-line collaborative voltage stability control is tested in the example 10-machine 39-node New England power system. Results of feasibility study from simulation are given considering the low-probability power system cascading faults.

Linear indicator for voltage collapse in power systems

A new linear indicator is presented together with a comparative study with other published works. The salient advantage of the linear characteristic is emphasised. The new index is tested utilising the IEEE 30 bus test power system

Evidence for two-phase regions in BST thin films from capacitance-voltage data

The Curie-Weiss plots of reciprocal dielectric constant versus temperature, in Ba0.5Sr0.5TiO3 films grown onto SrRuO3 lower electrodes by pulsed-laser deposition, show two minima below film thicknesses of 280 nm. This double minima implies possible mixed phases in the thin films. A graphical plot of capacitance for decreasing dc voltage versus that of increasing dc voltage shows a well-defined triangular shape for both Pb(Zr0.4Ti0.6)O-3 and SrBi2Ta2O9 thin films. However, for a 175-nm-thick Ba0.5Sr0.5TiO3 thin film, the plot shows an overlapping of two triangles, suggesting mixed phases. This graphical method appears to be effective in detecting structural subtleties in ferroelectric capacitors.

Demonstration of glycated insulin in human diabetic plasma and decreased biological activity assessed by euglycemic-hyperinsulinemic clamp technique in humans

The presence and biological significance of circulating glycated insulin has been evaluated by high-pressure liquid chromatography (HPLC), electrospray ionization mass spectrometry (ESI-MS), radioimmunoassay (RIA), receptor binding, and hyperinsulinemic-euglycemic clamp techniques. ESI-MS analysis of an HPLC-purified plasma pool from four male type 2 diabetic subjects (HbA(1e) 8.1 +/- 0.2%, plasma glucose 8.7 +/- 1.3 mmol/l [means +/- SE]) revealed two major insulin-like peaks with retention times of 14-16 min. After spectral averaging, the peak with retention time of 14.32 min exhibited a prominent triply charged (M+3H)(3+) species at 1,991.1 m/z, representing monoglycated insulin with an intact M-r of 5,970.3 Da. The second peak (retention time 15.70 min) corresponded to native insulin (M-r 5,807.6 Da), with the difference between the two peptides (162.7 Da) representing a single glucitol adduct (theoretical 164 Da). Measurement of glycated insulin in plasma of type 2 diabetic subjects by specific RIA gave circulating levels of 10.1 +/- 2.3 pmol/l, corresponding to -9% total insulin. Biological activity of pure synthetic monoglycated insulin (insulin B-chain Phe(1)-glucitol adduct) was evaluated in seven overnight-fasted healthy nonobese male volunteers using two-step euglycemic-hyperinsulinemic clamps (2 h at 16.6 mug (.) kg(-1) (.) min(-1), followed by 2 h at 83.0 mug (.) kg(-1) (.) min(-1); corresponding to 0.4 and 2.0 mU (.) kg(-1) (.) min(-1)). At the lower dose, the exogenons glucose infusion rates required to maintain euglycemia during steady state were significantly lower with glycated insulin (P

The role of the relative voltage and phase for frequency coupling in a dual-frequency capacitively coupled plasma

Frequency coupling in multifrequency discharges is a complex nonlinear interaction of the different frequency components. An alpha-mode low pressure rf capacitively coupled plasma operated simultaneously with two frequencies is investigated and the coupling of the two frequencies is observed to greatly influence the excitation and ionization within the discharge. Through this, plasma production and sustainment are dictated by the corresponding electron dynamics and can be manipulated through the dual-frequency sheath. These mechanisms are influenced by the relative voltage and also the relative phase of the two frequencies.

Idealised operation of zero-voltage-switching series-L/parallel-tuned Class-E power amplifier

An analysis of a modified series-L/parallel-tuned Class-E power amplifier is presented, which includes the effects that a shunt capacitance placed across the switching device will have on Class-E behaviour. In the original series L/parallel-tuned topology in which the output transistor capacitance is not inherently included in the circuit, zero-current switching (ZCS) and zero-current derivative switching (ZCDS) conditions should be applied to obtain optimum Class-E operation. On the other hand, when the output transistor capacitance is incorporated in the circuit, i.e. in the modified series-L/parallel-tuned topology, the ZCS and ZCDS would not give optimum operation and therefore zero-voltage-switching (ZVS) and zero-voltage-derivative switching (ZVDS) conditions should be applied instead. In the modified series-L/parallel-tuned Class-E configuration, the output-device inductance and the output-device output capacitance, both of which can significantly affect the amplifier's performance at microwave frequencies, furnish part, if not all, of the series inductance L and the shunt capacitance COUT, respectively. Further, when compared with the classic shunt-C/series-tuned topology, the proposed Class-E configuration offers some advantages in terms of 44% higher maximum operating frequency (fMAX) and 4% higher power-output capability (PMAX). As in the classic topology, the fMAX of the proposed amplifier circuit is reached when the output-device output capacitance furnishes all of the capacitance COUT, for a given combination of frequency, output power and DC supply voltage. It is also shown that numerical simulations agree well with theoretical predictions.

High tolerance to gate misalignment in low voltage gate-underlap double gate MOSFETs

.In this letter, we demonstrate for the first time that gate misalignment is not a critical limiting factor for low voltage operation in gate-underlap double gate (DG) devices. Our results show that underlap architecture significantly extends the tolerable limit of gate misalignment in 25 nm devices. DG MOSFETs with high degree of gate misalignment and optimal gate-underlap design can perform comparably or even better than self-aligned nonunderlap devices. Results show that spacer-to-straggle (s/sigma) ratio, a key design parameter for underlap devices, should be within the range of 2.3-3.0 to accommodate back gate misalignment. These results are very significant as the stringent process control requirements for achieving self-alignment in nanoscale planar DG MOSFETs are considerably relaxed

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Design and optimization of FinFETs for ultra-low-voltage analog applications

In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic de gain (A(vo)) and cutoff frequency (f(T)) for 60 and 30 nm FinFETs operated at low drive current (J(ds) = 5 mu A/mu m). The improved Avo and fT are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

Source/drain extension region engineering in FinFETs for low-voltage analog applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.