The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance

In this paper, the analogue performance of a 65 nm node double gate Sol (DGSOI) is qualitatively investigated using MixedMode simulation. The intrinsic resistance of the device is optimised by evaluating the impact of the source/drain engineering using variation of spacers and doping profile on the RF key figures of merit such as f(T), and f(MAX). It is evident that longer spacers, which approach the length of the gate offer better RF performance irrespective of the profile as long as the doping gradient at the gate edge is <7 nm/decade. Analytical expressions, which reflect the dependence of f(T), and fMAX on extrinsic source, drain and gate resistances R-S, R-D and R-G have been derived. While R-D and R-S have equal effect on f(T), R-D appears to be more influential than R-S in reducing f(MAX). The sensitivity of f(MAX) to R-S and R-D. has been shown to be greater than to R-G. (c) 2006 Elsevier Ltd. All rights reserved.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.

Analog performance of double gate SOI transistors

Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L-G reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f(T) and f(max) to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its fT was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted fmax in SG SOI was higher (similar to 40%) compared to DGSOI due to its lower capacitance.

Double potential step chronoamperometry at microdisk electrodes: simulating the case of unequal diffusion coefficients

An efficient approach to the simulation of the double potential step chronoamperometry at a microdisk electrode based on an exponentially expanding time grid and conformal mapping of the space is presented. The dimensionless second potential step flux data are included as a function of the first potential step duration and the ratio of the diffusion coefficients of the reacting species allowing instant analysis of the experimental double potential step chronoamperograms without a need for simulation. The values of the diffusion coefficients are determined for several test systems and found to be in good agreement with existing literature data. (C) 2004 Elsevier B.V. All rights reserved.

Deficiencies of double-strand break repair factors and effects on mutagenesis in directly gamma-irradiated and medium-mediated bystander human lymphoblastoid cells

Using RNA interference techniques to knock down key proteins in two major double-strand break (DSB) repair pathways (DNA-PKcs for nonhomologous end joining, NHEJ, and Rad54 for homologous recombination, HR), we investigated the influence of DSB repair factors on radiation mutagenesis at the autosomal thymidine kinase (TK) locus both in directly irradiated cells and in unirradiated bystander cells. We also examined the role of p53 (TP53) in these processes by using cells of three human lymphoblastoid cell lines from the same donor but with differing p53 status (TK6 is p53 wild-type, NH32 is p53 null, and WTK1 is p53 mutant). Our results indicated that p53 status did not affect either the production of radiation bystander mutagenic signals or the response to these signals. In directly irradiated cells, knockdown of DNA-PKcs led to an increased mutant fraction in WTK1 cells and decreased mutant fractions in TK6 and NH32 cells. In contrast, knockdown of DNA-PKcs led to increased mutagenesis in bystander cells regardless of p53 status. In directly irradiated cells, knockdown of Rad54 led to increased induced mutant fractions in WTK1 and NH32 cells, but the knockdown did not affect mutagenesis in p53 wild-type TK6 cells. In all cell lines, Rad54 knockdown had no effect on the magnitude of bystander mutagenesis. Studies with extracellular catalase confirmed the involvement of H2O2 in bystander signaling. Our results demonstrate that DSB repair factors have different roles in mediating mutagenesis in irradiated and bystander cells. (C) 2008 by Radiation Research Society.