921 resultados para Causal Loop Diagram


Relevância:

20.00% 20.00%

Publicador:

Resumo:

El presente trabajo se propone realizar un primer acercamiento al uso de los conectores causales como y porque en De la anarquía de Alberdi en relación al sistema Tema-Rema propuesto por la Lingüística Sistémico-Funcional. Si la lengua es un sistema de opciones, y la gramática ofrece dos opciones distintas para expresar la causa, es porque funcionalmente son diferentes. En nuestro corpus, cada uno de estos conectores organiza la información de manera distinta, puesto que como introduce causas en posición temática mientras porque tiende a introducir causas en posición remática. La elección de una u otra forma se encuentra en estrecha relación con las variables de campo, tenor y modo y con la información que se ofrece en cada momento del texto.

Relevância:

20.00% 20.00%

Publicador:

Resumo:

This paper examines the causalities in mean and variance between stock returns and Foreign Institutional Investment (FII) in India. The analysis in this paper applies the Cross Correlation Function approach from Cheung and Ng (1996), and uses daily data for the timeframe of January 1999 to March 2008 divided into two periods before and after May 2003. Empirical results showed that there are uni-directional causalities in mean and variance from stock returns to FII flows irrelevant of the sample periods, while the reverse causalities in mean and variance are only found in the period beginning with 2003. These results point to FII flows having exerted an impact on the movement of Indian stock prices during the more recent period.

Relevância:

20.00% 20.00%

Publicador:

Resumo:

In this paper, a novel and approach for obtaining 3D models from video sequences captured with hand-held cameras is addressed. We define a pipeline that robustly deals with different types of sequences and acquiring devices. Our system follows a divide and conquer approach: after a frame decimation that pre-conditions the input sequence, the video is split into short-length clips. This allows to parallelize the reconstruction step which translates into a reduction in the amount of computational resources required. The short length of the clips allows an intensive search for the best solution at each step of reconstruction which robustifies the system. The process of feature tracking is embedded within the reconstruction loop for each clip as opposed to other approaches. A final registration step, merges all the processed clips to the same coordinate frame

Relevância:

20.00% 20.00%

Publicador:

Resumo:

The main objective of ventilation systems in case of fire is the reduction of the possible consequences by achieving the best possible conditions for the evacuation of the users and the intervention of the emergency services. In the last years, the required quick response of the ventilation system, from normal to emergency mode, has been improved by the use of automatic and semi-automatic control systems, what reduces the response times through the support to the operators decision taking, and the use of pre-defined strategies. A further step consists on the use of closedloop algorithms, which takes into account not only the initial conditions but their development (air velocity, traffic situation, etc), optimizing the quality of the smoke control process

Relevância:

20.00% 20.00%

Publicador:

Resumo:

Abstract. This paper describes a new and original method for designing oscillators based on the Normalized Determinant Function (NDF) and Return Relations (RRT)- Firstly, a review of the loop-gain method will be performed. The loop-gain method pros, cons and some examples for exploring wrong solutions provided by this method will be shown. This method produces in some cases wrong solutions because some necessary conditions have not been fulfilled. The required necessary conditions to assure a right solution will be described. The necessity of using the NDF or the Transpose Return Relations (RRT), which are related with the True Loop-Gain, to test the additional conditions will be demonstrated. To conclude this paper, the steps for oscillator design and analysis, using the proposed NDF/RRj method, will be presented. The loop-gain wrong solutions will be compared with the NDF/RRj and the accuracy of this method to estimate the oscillation frequency and QL will be demonstrated. Some additional examples of plane reference oscillators (Z/Y/T), will be added and they will be analyzed with the new NDF/RRj proposed method, even these oscillators cannot be analyzed using the classic loop gain method.

Relevância:

20.00% 20.00%

Publicador:

Resumo:

Las arquitecturas jerárquicas de comunicación causal se presentan como una alternativa habitual para reducir el elevado tamaño de la información de control causal a enviar en cada mensaje, cuando la comunicación se realiza entre un subconjunto de procesos que pertenecen a un grupo muy numeroso. Sin embargo, en estas arquitecturas, los nodos intermedios de la jerarquía padecen un efecto indeseable denominado efecto convoy. Estos nodos intermedios tienden a generar ráfagas de envíos que sobrecargan tanto a los nodos de los niveles inferiores de la jerarquía como a la red, provocando pérdidas de mensajes y periodos entre ráfagas de infrautilización de la red. Este artículo presenta un servicio causal bidireccional sin contención que, aplicado a los nodos intermedios de la jerarquía, soluciona el efecto convoy. Este servicio causal sin contención entrega a la capa de aplicación y envía al sistema un mensaje sin esperar la entrega o el envío previo de mensajes que constituyen la historia causal del primero, por lo que evita las ráfagas de entrega y de envío de mensajes. La entrega de un mensaje va acompañada de un identificador causal, que es un número natural que indica el número de orden de ese mensaje en la secuencia causal total. El envío de un mensaje supone construir un vector causal válido a partir de un identiificador causal, que permita ordenar dicho mensaje en orden causal en el proceso receptor.

Relevância:

20.00% 20.00%

Publicador:

Resumo:

Let S be a set of n + m sites, of which n are red and have weight wR, and m are blue and weigh wB. The objective of this paper is to calculate the minimum value of wR such that the union of the red Voronoi cells in the weighted Voronoi diagram of S is a connected set. The problem is solved for the multiplicatively-weighted Voronoi diagram in O((n+m)^2 log(nm)) time and for the additively-weighted Voronoi diagram in O(nmlog(nm)) time.

Relevância:

20.00% 20.00%

Publicador:

Resumo:

This work evaluates a spline-based smoothing method applied to the output of a glucose predictor. Methods:Our on-line prediction algorithm is based on a neural network model (NNM). We trained/validated the NNM with a prediction horizon of 30 minutes using 39/54 profiles of patients monitored with the Guardian® Real-Time continuous glucose monitoring system The NNM output is smoothed by fitting a causal cubic spline. The assessment parameters are the error (RMSE), mean delay (MD) and the high-frequency noise (HFCrms). The HFCrms is the root-mean-square values of the high-frequency components isolated with a zero-delay non-causal filter. HFCrms is 2.90±1.37 (mg/dl) for the original profiles.

Relevância:

20.00% 20.00%

Publicador:

Resumo:

Functional validation of complex digital systems is a hard and critical task in the design flow. In particular, when dealing with communication systems, like Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband (MB-OFDM UWB), the design decisions taken during the process have to be validated at different levels in an easy way. In this work, a unified algorithm-architecture-circuit co-design environment for this type of systems, to be implemented in FPGA, is presented. The main objective is to find an efficient methodology for designing a configurable optimized MB-OFDM UWB system by using as few efforts as possible in verification stage, so as to speed up the development period. Although this efficient design methodology is tested and considered to be suitable for almost all types of complex FPGA designs, we propose a solution where both the circuit and the communication channel are tested at different levels (algorithmic, RTL, hardware device) using a common testbench.