Application of fractional calculus in engineering

Fractional Calculus (FC) goes back to the beginning of the theory of differential calculus. Nevertheless, the application of FC just emerged in the last two decades. It has been recognized the advantageous use of this mathematical tool in the modelling and control of many dynamical systems. Having these ideas in mind, this paper discusses a FC perspective in the study of the dynamics and control of several systems. The paper investigates the use of FC in the fields of controller tuning, legged robots, electrical systems and digital circuit synthesis.

An embedded 1149.4 extension to support mixed-signal debugging

Debugging electronic circuits is traditionally done with bench equipment directly connected to the circuit under debug. In the digital domain, the difficulties associated with the direct physical access to circuit nodes led to the inclusion of resources providing support to that activity, first at the printed circuit level, and then at the integrated circuit level. The experience acquired with those solutions led to the emergence of dedicated infrastructures for debugging cores at the system-on-chip level. However, all these developments had a small impact in the analog and mixed-signal domain, where debugging still depends, to a large extent, on direct physical access to circuit nodes. As a consequence, when analog and mixed-signal circuits are integrated as cores inside a system-on-chip, the difficulties associated with debugging increase, which cause the time-to-market and the prototype verification costs to also increase. The present work considers the IEEE1149.4 infrastructure as a means to support the debugging of mixed-signal circuits, namely to access the circuit nodes and also an embedded debug mechanism named mixed-signal condition detector, necessary for watch-/breakpoints and real-time analysis operations. One of the main advantages associated with the proposed solution is the seamless migration to the system-on-chip level, as the access is done through electronic means, thus easing debugging operations at different hierarchical levels.

Reverse problem-based learning - a case study with a Braille machine

Engineering Education includes not only teaching theoretical fundamental concepts but also its verification during practical lessons in laboratories. The usual strategies to carry out this action are frequently based on Problem Based Learning, starting from a given state and proceeding forward to a target state. The possibility or the effectiveness of this procedure depends on previous states and if the present state was caused or resulted from earlier ones. This often happens in engineering education when the achieved results do not match the desired ones, e.g. when programming code is being developed or when the cause of the wrong behavior of an electronic circuit is being identified. It is thus important to also prepare students to proceed in the reverse way, i.e. given a start state generate the explanation or even the principles that underlie it. Later on, this sort of skills will be important. For instance, to a doctor making a patient?s story or to an engineer discovering the source of a malfunction. This learning methodology presents pedagogical advantages besides the enhanced preparation of students to their future work. The work presented on his document describes an automation project developed by a group of students in an engineering polytechnic school laboratory. The main objective was to improve the performance of a Braille machine. However, in a scenario of Reverse Problem-Based learning, students had first to discover and characterize the entire machine's function before being allowed (and being able) to propose a solution for the existing problem.

Automated design of microwave discrete tuning differential capacitance circuits in Si-integrated technologies

A genetic algorithm used to design radio-frequency binary-weighted differential switched capacitor arrays (RFDSCAs) is presented in this article. The algorithm provides a set of circuits all having the same maximum performance. This article also describes the design, implementation, and measurements results of a 0.25 lm BiCMOS 3-bit RFDSCA. The experimental results show that the circuit presents the expected performance up to 40 GHz. The similarity between the evolutionary solutions, circuit simulations, and measured results indicates that the genetic synthesis method is a very useful tool for designing optimum performance RFDSCAs.

Some applications of fractional calculus in engineering

Fractional Calculus FC goes back to the beginning of the theory of differential calculus. Nevertheless, the application of FC just emerged in the last two decades, due to the progress in the area of chaos that revealed subtle relationships with the FC concepts. In the field of dynamical systems theory some work has been carried out but the proposed models and algorithms are still in a preliminary stage of establishment. Having these ideas in mind, the paper discusses FC in the study of system dynamics and control. In this perspective, this paper investigates the use of FC in the fields of controller tuning, legged robots, redundant robots, heat diffusion, and digital circuit synthesis.

Anti-Corrosion performance of a new silane coating for corrosion protection of AZ31 Magnesium alloy in Hank’s solution

Mg alloys can be used as bioresorsable metallic implants. However, the high corrosion rate of magnesium alloys has limited their biomedical applications. Although Mg ions are essential to the human body, an excess may cause undesirable health effects. Therefore, surface treatments are required to enhance the corrosion resistance of magnesium parts, decreasing its rate to biocompatible levels and allowing its safe application as bioresorbable metallic implants. The application of biocompatible silane coatings is envisaged as a suitable strategy for retarding the corrosion process of magnesium alloys. In the current work, a new glycidoxypropyltrimethoxysilane (GPTMS) based coating was tested on AZ31 magnesium substrates subjected to different surface conditioning procedures before coating deposition. The surface conditioning included a short etching with hydrofluoric acid (HF) or a dc polarisation in alkaline electrolyte. The silane coated samples were immersed in Hank's solution and the protective performance of the coating was studied through electrochemical impedance spectroscopy (EIS). The EIS data was treated by new equivalent circuit models and the results revealed that the surface conditioning process plays a key role in the effectiveness of the silane coating. The HF treated samples led to the highest impedance values and delayed the coating degradation, compared to the mechanically polished samples or to those submitted to dc polarisation.

Experimental apparatus for finger ECG biometrics

Current Electrocardiographic (ECG) signal acquisition methods are generally highly intrusive, as they involve the use of pre-gelled electrodes and cabled sensors placed directly on the person, at the chest or limbs level. Moreover, systems that make use of alternative conductive materials to overcome this issue, only provide heart rate information and not the detailed signal itself. We present a comparison and evaluation of two types of dry electrodes as interface with the skin, targeting wearable and low intrusiveness applications, which enable ECG measurement without the need for any apparatus permanently fitted to the individual. In particular, our approach is targeted at ECG biometrics using signals collected at the hand or finger level. A custom differential circuit with virtual ground was also developed for enhanced usability. Our work builds upon the current stateof-the-art in sensoring devices and processing tools, and enables novel data acquisition settings through the use of dry electrodes. Experimental evaluation was performed for Ag/AgCl and Electrolycra materials, and results show that both materials exhibit adequate performance for the intended application.

From design-for-test to design-for-debug-and-test: analysis of requirements and limitations for 1149.1

The increasing complexity of VLSI circuits and the reduced accessibility of modern packaging and mounting technologies restrict the usefulness of conventional in-circuit debugging tools, such as in-circuit emulators for microprocessors and microcontrollers. However, this same trend enables the development of more complex products, which in turn require more powerful debugging tools. These conflicting demands could be met if the standard scan test infrastructures now common in most complex components were able to match the debugging requirements of design verification and prototype validation. This paper analyses the main debug requirements in the design of microprocessor-based applications and the feasibility of their implementation using the mandatory, optional and additional operating modes of the standard IEEE 1149.1 test infrastructure.

Light-activated amplification in SiC Tandem devices: A capacitive active filter model

Characteristics of tunable wavelength pi'n/pin filters based on a-SiC:H multilayered stacked cells are studied both experimentally and theoretically. Results show that the device combines the demultiplexing operation with the simultaneous photodetection and self amplification of the signal. An algorithm to decode the multiplex signal is established. A capacitive active band-pass filter model is presented and supported by an electrical simulation of the state variable filter circuit. Experimental and simulated results show that the device acts as a state variable filter. It combines the properties of active high-pass and low-pass filter sections into a capacitive active band-pass filter using a changing capacitance to control the power delivered to the load.

Reliability and availability in reconfigurable computing: a basis for a common solution

Dynamically reconfigurable SRAM-based field-programmable gate arrays (FPGAs) enable the implementation of reconfigurable computing systems where several applications may be run simultaneously, sharing the available resources according to their own immediate functional requirements. To exclude malfunctioning due to faulty elements, the reliability of all FPGA resources must be guaranteed. Since resource allocation takes place asynchronously, an online structural test scheme is the only way of ensuring reliable system operation. On the other hand, this test scheme should not disturb the operation of the circuit, otherwise availability would be compromised. System performance is also influenced by the efficiency of the management strategies that must be able to dynamically allocate enough resources when requested by each application. As those resources are allocated and later released, many small free resource blocks are created, which are left unused due to performance and routing restrictions. To avoid wasting logic resources, the FPGA logic space must be defragmented regularly. This paper presents a non-intrusive active replication procedure that supports the proposed test methodology and the implementation of defragmentation strategies, assuring both the availability of resources and their perfect working condition, without disturbing system operation.

Particle swarm design of digital circuits

Swarm Intelligence (SI) is the property of a system whereby the collective behaviors of (unsophisticated) agents interacting locally with their environment cause coherent functional global patterns to emerge. Particle swarm optimization (PSO) is a form of SI, and a population-based search algorithm that is initialized with a population of random solutions, called particles. These particles are flying through hyperspace and have two essential reasoning capabilities: their memory of their own best position and knowledge of the swarm's best position. In a PSO scheme each particle flies through the search space with a velocity that is adjusted dynamically according with its historical behavior. Therefore, the particles have a tendency to fly towards the best search area along the search process. This work proposes a PSO based algorithm for logic circuit synthesis. The results show the statistical characteristics of this algorithm with respect to number of generations required to achieve the solutions. It is also presented a comparison with other two Evolutionary Algorithms, namely Genetic and Memetic Algorithms.

Electrochemical and analytical investigation of passive films formed on stainless steels in alkaline media

Passive films were grown in potentiodynamic mode, by cyclic voltammetry on AISI 316 and AISI 304 stainless steels. The composition of these films was investigated by X-ray photoelectron spectroscopy (XPS). The electrochemical behaviour and the chemical composition of the passive films formed by cyclic voltammetry were compared to those of films grown under natural conditions (by immersion at open circuit potential, OCP) in alkaline solutions simulating concrete. The study included the effect of pH of the electrolyte and the effect of the presence of chloride ions. The XPS results revealed important changes in the passive film composition, which becomes enriched in chromium and depleted in magnetite as the pH decreases. On the other hand, the presence of chlorides promotes a more oxidised passive layer. The XPS results also showed relevant differences on the composition of the oxide layers for the films formed under cyclic voltammetry and/or under OCP.

Determinação do teor de compostos aromáticos policíclicos de óleos minerais isolantes para transformadores

Mestrado em Engenharia Química - Ramo Optimização Energética na Indústria Química

Sistema didáctico de baixo custo com FPGA de alta densidade

O uso das Field-Programmable Gate Array tem crescido de forma exponencial. Com isto dito, é importante que os engenheiros electrotécnicos estejam familiarizados com este tipo de tecnologia. Foi com o intuído de passar estas valências para os alunos do ISEP, que surgiu a ideia de criar um sistema didáctico, que permitisse ao alunos aprender a trabalhar com estes dispositivos. O seguinte trabalho iniciou-se com base num estudo das características destes dispositivos e das suas potencialidades, seguido de uma avaliação do que o mercado tem para oferecer. Posteriormente, com base em toda a informação reunida, foi definida a arquitectura do sistema, que levou selecção de dispositivos a incluir no mesmo, e culminando na concepção do esquema eléctrico do sistema e da placa de circuito impresso correspondente ao protótipo do mesmo. As principais directivas para este projecto foram o uso de uma FPGA de alta densidade e a concepção da ferramenta com o custo de projecto o mais reduzido possível.

Marx-Type solid-state bipolar modulator topologies: Performance comparison

The operation of generalized Marx-type solid-state bipolar modulators is discussed and compared with simplified Marx-derived circuits, to evaluate their capability to deal with various load conditions. A comparative analysis on the number of switches per cell, fiber optic trigger count, losses, and switch hold-off voltages has been made. A circuit topology is obtained as a compromise in terms of operating performance, trigger simplicity, and switching losses. A five-stage laboratory prototype of this circuit has been assembled using 1200 V insulated gate bipolar transistors (IGBTs) and diodes, operating with 1000 V dc input voltage and 1 kHz frequency, giving 5 kV bipolar pulses, with 2.5 mu s pulse width and 5 mu s relaxation time into resistive, capacitive, and inductive loads.