Influence of the composition of natural gas-hydrogen blends (HCNG) on performance an CO2 emissions of a spark ignition engine

Addition of hydrogen to natural gas could be a short-term alternative to nowadays fossil fuels as the emissions of greenhouse gases may be reduced. The aim of this study is to evaluate the performance and emissions of a park ignition engine fuelled with pure natural gas, pure hydrogen and different blends of hydrogen and natural gas (HCNG). The increase of the hydrogen fraction leads to variations in the cylinder pressure and CO2 emissions. In this work, a combustion model based on thermodynamic equations is used considering separated zones for the burned and unburned gases. The results show that the maximum cylinder pressure gets higher as the fraction of hydrogen in the blend increases. The presence of hydrogen in the blend leads to a drecrease in the CO2 emissions. Due to hydrogen properties, leaner fuel-air mixtures can be used along with the appropiate spark timing, leading to an engine emissions improvement without a performance worsening.

Dry cooling with night cool storage to enhance solar power plants performance in extreme conditions areas

Solar thermal power plants are usually installed in locations with high yearly average solar radiation, often deserts. In such conditions, cooling water required for thermodynamic cycles is rarely available. Moreover, when solar radiation is high, ambient temperature is very high as well; this leads to excessive condensation temperature, especially when air-condensers are used, and decreases the plant efficiency. However, temperature variation in deserts is often very high, which drives to relatively low temperatures during the night. This fact can be exploited with the use of a closed cooling system, so that the coolant (water) is chilled during the night and store. Chilled water is then used during peak temperature hours to cool the condenser (dry cooling), thus enhancing power output and efficiency. The present work analyzes the performance improvement achieved by night thermal cool storage, compared to its equivalent air cooled power plant. Dry cooling is proved to be energy-effective for moderately high day–night temperature differences (20 °C), often found in desert locations. The storage volume requirement for different power plant efficiencies has also been studied, resulting on an asymptotic tendency.

Analysis of Proseds bare-tether performance

NASA's tether experiment ProSEDS will be placed in orbit on board a Delta-II rocket in early 2003. ProSEDS will test bare-tether electron collection, deorbiting of the rocket second stage, and the system dynamic stability. ProSEDS performance will vary both because ambient conditions change along the orbit and because tether-circuit parameters follow a step by step sequence in the current operating cycle. In this work we discuss how measurements of tether current and bias, plasma density, and deorbiting rate can be used to check the OML law for current collection. We review circuit bulk elements; characteristic lengths and energies that determine collection (tether radius, electron thermal gyroradius and Debye length, particle temperatures, tether bias, ion ram energy); and lengths determining current and bias profiles along the tether (extent of magnetic self-field, a length gauging ohmic versus collection impedances, tether length). The analysis serves the purpose of estimating ProSEDS behavior in orbit and fostering our ability for extrapolating ProSEDS flight data to different tether and environmental conditions.

Performance of UV-enhanced PMMA fresnel lenses and impact on LCOE

Tiny increases in the transmittance of optical materials within a CPV module can have an important impact on the economy of a plant. This is certainly true in systems comprising multi-junction solar cells, whose high performance, based on a balanced photocurrent generation among the series-connected junctions, is very sensitive to spectrum variations. Every efficiency point gained causes not only an increase in the kilowatts hour produced, but a higher benefit on it, since the difference between electricity tariff and Levelized Cost of Electricity (LCOE) rises. This work studies the impact on the LCOE of a plant based on modules comprising PMMA lenses of two different types, standard UV blocking grade which is normally used for outdoor applications at high DNI climate and a specialty stabilized UV-enhanced transmittance acrylic (see Figure 1). Energy production will be compared for these two systems throughout the year at different sites to analyze when (season, time of the day) and where the usage of the enhanced PMMA is justified.

Improvement of the Dynamic Performance of a Multiphase Current Controlled Buck Converter using an Auxiliary Synchronous Buck Converter as an Additional Energy Path

This work is related to the output impedance improvement of a Multiphase Buck converter with Peak Current Mode Control (PCMC) by means of introducing an additional power path that virtually increases the output capacitance during transients. Various solutions that can be employed to improve the dynamic behavior of the converter system exist, but nearly all solutions are developed for a Single Phase Buck converter with Voltage Mode Control (VMC), while in the VRM applications, due to the high currents, the system is usually implemented as a Multiphase Buck Converter with Current Mode Control. The additional energy path, as presented here, is introduced with the Output Impedance Correction Circuit (OICC) based on the Controlled Current Source (CCS). The OICC is used to inject or extract a current n-1 times larger than the output capacitor current, thus virtually increasing n times the value of the output capacitance during the transients. Furthermore, this work extends the OICC concept to a Multiphase Buck Converter system while comparing proposed solution with the system that has n times bigger output capacitor. In addition, the OICC is implemented as a Synchronous Buck Converter with PCMC, thus reducing its influence on the system efficiency.

Testing the performance of a green wall system on an experimental building in the summer

It is known that a green wall brings some advantages to a building. It constitutes a barrier against solar radiation, thus decreasing and delaying the incoming heat flux. The aim of this study is to quantify such advantages through analytical comparison between two facades, a vegetal facade and a conventional facade. Both were highly insulated (U-value = 0.3 W/m2K) and installed facing south on the same building in the central territory of Spain. In order to compare their thermal trend, a series of sensors were used to register superficial and indoor air temperature. The work was carried out between 17th August 2012 and 1st October 2012, with a temperature range of 12°C-36°C and a maximum horizontal radiation of 1020 W/m2. Results show that the indoor temperature of the green wall module was lower than the other. Besides, comparing superficial outdoor and indoor temperatures of the two walls to outdoor air temperatures, it was noticed that, due to the shading plants, the green wall superficial temperature was 5 °C lower on the facade, while the bare wall temperature was 15 °C higher. The living wall module temperature was 1.6 °C lower than the outdoor, while the values of the conventional one were similar to the outdoor air temperature.

Development of an Elevated Temperature Loop Heat Pipe for Space Applications and Investigation of Non Condensable Gas Impact on its Performance

Un caloducto en bucle cerrado o Loop Heat Pipe (LHP) es un dispositivo de transferencia de calor cuyo principio de operación se basa en la evaporación/condensación de un fluido de trabajo, que es bombeado a través de un circuito cerrado gracias a fuerzas de capilaridad. Gracias a su flexibilidad, su baja masa y su mínimo (incluso nulo) consumo de potencia, su principal aplicación ha sido identificada como parte del subsistema de control térmico de vehículos espaciales. En el presente trabajo se ha desarrollado un LHP capaz de funcionar eficientemente a temperaturas de hasta 125 oC, siguiendo la actual tendencia de los equipos a bordo de satélites de incrementar su temperatura de operación. En la selección del diseño optimo para dicho LHP, la compatibilidad entre materiales y fluido de trabajo se identificó como uno de los puntos clave. Para seleccionar la mejor combinación, se llevó a cabo una exhaustiva revisión del estado del arte, además de un estudio especifico que incluía el desarrollo de un banco de ensayos de compatibilidad. Como conclusión, la combinación seleccionada como la candidata idónea para ser integrada en el LHP capaz de operar hasta 125 oC fue un evaporador de acero inoxidable, líneas de titanio y amoniaco como fluido de trabajo. En esa línea se diseñó y fabricó un prototipo para ensayos y se desarrolló un modelo de simulación con EcosimPro para evaluar sus prestaciones. Se concluyó que el diseño era adecuado para el rango de operación definido. La incompatibilidad entre el fluido de trabajo y los materiales del LHP está ligada a la generación de gases no condensables. Para un estudio más detallado de los efectos de dichos gases en el funcionamiento del LHP se analizó su comportamiento con diferentes cantidades de nitrógeno inyectadas en su cámara de compensación, simulando un gas no condensable formado en el interior del dispositivo. El estudio se basó en el análisis de las temperaturas medidas experimentalmente a distintos niveles de potencia y temperatura de sumidero o fuente fría. Adicionalmente, dichos resultados se compararon con las predicciones obtenidas por medio del modelo en EcosimPro. Las principales conclusiones obtenidas fueron dos. La primera indica que una cantidad de gas no condensable más de dos veces mayor que la cantidad generada al final de la vida de un satélite típico de telecomunicaciones (15 años) tiene efectos casi despreciables en el funcionamiento del LHP. La segunda es que el principal efecto del gas no condensable es una disminución de la conductancia térmica, especialmente a bajas potencias y temperaturas de sumidero. El efecto es más significativo cuanto mayor es la cantidad de gas añadida. Asimismo, durante la campaña de ensayos se observó un fenómeno no esperado para grandes cantidades de gas no condensable. Dicho fenómeno consiste en un comportamiento oscilatorio, detectado tanto en los ensayos como en la simulación. Este efecto es susceptible de una investigación más profunda y los resultados obtenidos pueden constituir la base para dicha tarea. ABSTRACT Loop Heat Pipes (LHPs) are heat transfer devices whose operating principle is based on the evaporation/condensation of a working fluid, and which use capillary pumping forces to ensure the fluid circulation. Thanks to their flexibility, low mass and minimum (even null) power consumption, their main application has been identified as part of the thermal control subsystem in spacecraft. In the present work, an LHP able to operate efficiently up to 125 oC has been developed, which is in line with the current tendency of satellite on-board equipment to increase their operating temperatures. In selecting the optimal LHP design for the elevated temperature application, the compatibility between the materials and working fluid has been identified as one of the main drivers. An extensive literature review and a dedicated trade-off were performed, in order to select the optimal combination of fluids and materials for the LHP. The trade-off included the development of a dedicated compatibility test stand. In conclusion, the combination of stainless steel evaporator, titanium piping and ammonia as working fluid was selected as the best candidate to operate up to 125 oC. An LHP prototype was designed and manufactured and a simulation model in EcosimPro was developed to evaluate its performance. The first conclusion was that the defined LHP was suitable for the defined operational range. Incompatibility between the working fluid and LHP materials is linked to Non Condensable Gas (NCG) generation. Therefore, the behaviour of the LHP developed with different amounts of nitrogen injected in its compensation chamber to simulate NCG generation, was analyzed. The LHP performance was studied by analysis of the test results at different temperatures and power levels. The test results were also compared to simulations in EcosimPro. Two additional conclusions can be drawn: (i) the effects of an amount of more than two times the expected NCG at the end of life of a typical telecommunications satellite (15 years) is almost negligible on the LHP operation, and (ii) the main effect of the NCG is a decrease in the LHP thermal conductance, especially at low temperatures and low power levels. This decrease is more significant with the progressive addition of NCG. An unexpected phenomenon was observed in the LHP operation with large NCG amounts. Namely, an oscillatory behaviour, which was observed both in the tests and the simulation. This effect provides the basis for further studies concerning oscillations in LHPs.

Passive design strategies and performance of Net Energy Plus Houses

The first step in order to comply with the European Union goals of Near to Zero Energy Buildings is to reduce the energy consumption in buildings. Most of the building consumption is related to the use of active systems to maintain the interior comfort. Passive design strategies contribute to improve the interior comfort conditions, increasing the energy efficiency in buildings and reducing their energy consumption. In this work, an analysis of the passive strategies used in Net Energy Plus Houses has been made. The participating houses of the Solar Decathlon Europe 2012 competition were used as case studies. The passive design strategies of these houses were compared with the annual simulations, and the competition monitored data, especially during the Passive Monitored Period. The analysis included the thermal properties of the building envelope, geometric parameters, ratios and others passive solutions such as Thermal Energy Storage systems, evaporative cooling, night ventilation, solar gains and night sky radiation cooling. The results reflect the impact of passive design strategies on the houses' comfort and efficiency, as well as their influence in helping to achieve the Zero Energy Buildings category.

Teamwork, motivational profiles and academic performance in computer science engineering

The present work is aimed at discussing several issues related to the teamwork generic competence, motivational profiles and academic performance. In particular, we study the improvement of teamwork attitude, the predominant types of motivation in different contexts and some correlations among these three components of the learning process. The above-mentioned aspects are of great importance. Currently, the professional profile of engineers has a strong teamwork component and the motivational profile of students determines both their tendencies when they come to work as part of a team, as well as their performance at work. Taking these issues into consideration, we suggest four hypotheses: (H1) students improve their teamwork capacity through specific training and carrying out of a set of activities integrated into an active learning process; (H2) students with higher mastery motivation have a better attitude towards teamwork; (H3) students with different types of motivations reach different levels of academic performance; and (H4) students show different motivation profiles in different circumstances: type of courses, teaching methodologies, different times of the learning process. This study was carried out with Computer Science Engineering students from two Spanish universities. The first results point to an improvement in teamwork competence of students if they have previously received specific training in facets of that competence. Other results indicate that there is a correlation between the motivational profiles of students and their perception of teamwork competence. Finally, results point to a clear relationship between some kind of motivation and academic performance. In particular, four kinds of motivation are analyzed and students are classified into two groups according to them. After analyzing several marks obtained in compulsory courses, we perceive that those students that show higher motivation for avoiding failure obtain, in general, worse academic performance.

On the harmonic analysis of cup anemometer rotation speed: A principle to monitor performance and maintenance status of rotating meteorological sensors

The calibration results of one anemometer equipped with several rotors, varying their size, were analyzed. In each case, the 30-pulses pert turn output signal of the anemometer was studied using Fourier series decomposition and correlated with the anemometer factor (i.e., the anemometer transfer function). Also, a 3-cup analytical model was correlated to the data resulting from the wind tunnel measurements. Results indicate good correlation between the post-processed output signal and the working condition of the cup anemometer. This correlation was also reflected in the results from the proposed analytical model. With the present work the possibility of remotely checking cup anemometer status, indicating the presence of anomalies and, therefore, a decrease on the wind sensor reliability is revealed.

High Intensity Low Temperature (HILT) performance of space concentrator GaInP/GaInAs/Ge MJ SCs

In the work, the results of an investigation of GaInP/GaInAs/Ge MJ SCs intended for converting concentrated solar radiation, when operating at low temperatures (down to -190 degrees C) are presented. A kink of the cell I-V characteristic has been observed in the region close to V-oc starting from -20 degrees C at operation under concentrated sunlight. The causes for its occurrence have been analyzed and the reasons for formation of a built-in potential barrier for majority charge carriers at the n-GaInP/n-Ge isotype hetero-interface are discussed. The effect of charge carrier transport in n-GaInP/n-p Ge heterostructures on MJ SC output characteristics at low temperatures has been studied including EL technique.

Performance and Professional Skills in an Online Java Programming Course for Engineering Students

The main purpose of this work is to describe the case of an online Java Programming course for engineering students to learn computer programming and to practice other non-technicalabilities: online training, self-assessment, teamwork and use of foreign languages. It is important that students develop confidence and competence in these skills, which will be required later in their professional tasks and/or in other engineering courses (life-long learning). Furthermore, this paper presents the pedagogical methodology, the results drawn from this experience and an objective performance comparison with another conventional (face-to-face) Java course.

Energy and Lighting Performance of Buildings in the Neighbourhood Ciudad de los Angeles, Before and After Refurbishing.

The Spanish Ministry of Economy and Competitiveness is funding the SHERIF Research Project, which falls under the INNPACTO pr ogram. This project aims to increase the rate of the existing building refurbishment fro m the energy efficiency point of view by designing a facade system that must be an economica l, flexible and integrated solution 1 . Under this project has been performing several task s regarding the constructive characterization and energy evaluation of the therm al behaviour of facades on existing buildings . In order to perform the latter task, in which this article will focus, has been developing a survey of various buildings in the nei ghbourhood Ciudad de los Angeles, which has as main objective the comparison between the ac tual energy and light behaviour of different buildings, prior and posterior to any ref urbishment works have been undertaken. The evaluation of the actual performance of buildin gs before and after being refurbished is aimed to determine the impact of the work developed as well as learn from the work performed for future interventions.

A Dynamically Adaptable Image Processing Application Trading Off Between High Performance, Consumption and Dependability in Real Time

As embedded systems evolve, problems inherent to technology become important limitations. In less than ten years, chips will exceed the maximum allowed power consumption affecting performance, since, even though the resources available per chip are increasing, frequency of operation has stalled. Besides, as the level of integration is increased, it is difficult to keep defect density under control, so new fault tolerant techniques are required. In this demo work, a new dynamically adaptable virtual architecture (ARTICo3) to allow dynamic and context-aware use of resources is implemented in a high performance Wireless Sensor node (HiReCookie) to perform an image processing application.

Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems

Esta tesis doctoral se enmarca dentro del campo de los sistemas embebidos reconfigurables, redes de sensores inalámbricas para aplicaciones de altas prestaciones, y computación distribuida. El documento se centra en el estudio de alternativas de procesamiento para sistemas embebidos autónomos distribuidos de altas prestaciones (por sus siglas en inglés, High-Performance Autonomous Distributed Systems (HPADS)), así como su evolución hacia el procesamiento de alta resolución. El estudio se ha llevado a cabo tanto a nivel de plataforma como a nivel de las arquitecturas de procesamiento dentro de la plataforma con el objetivo de optimizar aspectos tan relevantes como la eficiencia energética, la capacidad de cómputo y la tolerancia a fallos del sistema. Los HPADS son sistemas realimentados, normalmente formados por elementos distribuidos conectados o no en red, con cierta capacidad de adaptación, y con inteligencia suficiente para llevar a cabo labores de prognosis y/o autoevaluación. Esta clase de sistemas suele formar parte de sistemas más complejos llamados sistemas ciber-físicos (por sus siglas en inglés, Cyber-Physical Systems (CPSs)). Los CPSs cubren un espectro enorme de aplicaciones, yendo desde aplicaciones médicas, fabricación, o aplicaciones aeroespaciales, entre otras muchas. Para el diseño de este tipo de sistemas, aspectos tales como la confiabilidad, la definición de modelos de computación, o el uso de metodologías y/o herramientas que faciliten el incremento de la escalabilidad y de la gestión de la complejidad, son fundamentales. La primera parte de esta tesis doctoral se centra en el estudio de aquellas plataformas existentes en el estado del arte que por sus características pueden ser aplicables en el campo de los CPSs, así como en la propuesta de un nuevo diseño de plataforma de altas prestaciones que se ajuste mejor a los nuevos y más exigentes requisitos de las nuevas aplicaciones. Esta primera parte incluye descripción, implementación y validación de la plataforma propuesta, así como conclusiones sobre su usabilidad y sus limitaciones. Los principales objetivos para el diseño de la plataforma propuesta se enumeran a continuación: • Estudiar la viabilidad del uso de una FPGA basada en RAM como principal procesador de la plataforma en cuanto a consumo energético y capacidad de cómputo. • Propuesta de técnicas de gestión del consumo de energía en cada etapa del perfil de trabajo de la plataforma. •Propuestas para la inclusión de reconfiguración dinámica y parcial de la FPGA (por sus siglas en inglés, Dynamic Partial Reconfiguration (DPR)) de forma que sea posible cambiar ciertas partes del sistema en tiempo de ejecución y sin necesidad de interrumpir al resto de las partes. Evaluar su aplicabilidad en el caso de HPADS. Las nuevas aplicaciones y nuevos escenarios a los que se enfrentan los CPSs, imponen nuevos requisitos en cuanto al ancho de banda necesario para el procesamiento de los datos, así como en la adquisición y comunicación de los mismos, además de un claro incremento en la complejidad de los algoritmos empleados. Para poder cumplir con estos nuevos requisitos, las plataformas están migrando desde sistemas tradicionales uni-procesador de 8 bits, a sistemas híbridos hardware-software que incluyen varios procesadores, o varios procesadores y lógica programable. Entre estas nuevas arquitecturas, las FPGAs y los sistemas en chip (por sus siglas en inglés, System on Chip (SoC)) que incluyen procesadores embebidos y lógica programable, proporcionan soluciones con muy buenos resultados en cuanto a consumo energético, precio, capacidad de cómputo y flexibilidad. Estos buenos resultados son aún mejores cuando las aplicaciones tienen altos requisitos de cómputo y cuando las condiciones de trabajo son muy susceptibles de cambiar en tiempo real. La plataforma propuesta en esta tesis doctoral se ha denominado HiReCookie. La arquitectura incluye una FPGA basada en RAM como único procesador, así como un diseño compatible con la plataforma para redes de sensores inalámbricas desarrollada en el Centro de Electrónica Industrial de la Universidad Politécnica de Madrid (CEI-UPM) conocida como Cookies. Esta FPGA, modelo Spartan-6 LX150, era, en el momento de inicio de este trabajo, la mejor opción en cuanto a consumo y cantidad de recursos integrados, cuando además, permite el uso de reconfiguración dinámica y parcial. Es importante resaltar que aunque los valores de consumo son los mínimos para esta familia de componentes, la potencia instantánea consumida sigue siendo muy alta para aquellos sistemas que han de trabajar distribuidos, de forma autónoma, y en la mayoría de los casos alimentados por baterías. Por esta razón, es necesario incluir en el diseño estrategias de ahorro energético para incrementar la usabilidad y el tiempo de vida de la plataforma. La primera estrategia implementada consiste en dividir la plataforma en distintas islas de alimentación de forma que sólo aquellos elementos que sean estrictamente necesarios permanecerán alimentados, cuando el resto puede estar completamente apagado. De esta forma es posible combinar distintos modos de operación y así optimizar enormemente el consumo de energía. El hecho de apagar la FPGA para ahora energía durante los periodos de inactividad, supone la pérdida de la configuración, puesto que la memoria de configuración es una memoria volátil. Para reducir el impacto en el consumo y en el tiempo que supone la reconfiguración total de la plataforma una vez encendida, en este trabajo, se incluye una técnica para la compresión del archivo de configuración de la FPGA, de forma que se consiga una reducción del tiempo de configuración y por ende de la energía consumida. Aunque varios de los requisitos de diseño pueden satisfacerse con el diseño de la plataforma HiReCookie, es necesario seguir optimizando diversos parámetros tales como el consumo energético, la tolerancia a fallos y la capacidad de procesamiento. Esto sólo es posible explotando todas las posibilidades ofrecidas por la arquitectura de procesamiento en la FPGA. Por lo tanto, la segunda parte de esta tesis doctoral está centrada en el diseño de una arquitectura reconfigurable denominada ARTICo3 (Arquitectura Reconfigurable para el Tratamiento Inteligente de Cómputo, Confiabilidad y Consumo de energía) para la mejora de estos parámetros por medio de un uso dinámico de recursos. ARTICo3 es una arquitectura de procesamiento para FPGAs basadas en RAM, con comunicación tipo bus, preparada para dar soporte para la gestión dinámica de los recursos internos de la FPGA en tiempo de ejecución gracias a la inclusión de reconfiguración dinámica y parcial. Gracias a esta capacidad de reconfiguración parcial, es posible adaptar los niveles de capacidad de procesamiento, energía consumida o tolerancia a fallos para responder a las demandas de la aplicación, entorno, o métricas internas del dispositivo mediante la adaptación del número de recursos asignados para cada tarea. Durante esta segunda parte de la tesis se detallan el diseño de la arquitectura, su implementación en la plataforma HiReCookie, así como en otra familia de FPGAs, y su validación por medio de diferentes pruebas y demostraciones. Los principales objetivos que se plantean la arquitectura son los siguientes: • Proponer una metodología basada en un enfoque multi-hilo, como las propuestas por CUDA (por sus siglas en inglés, Compute Unified Device Architecture) u Open CL, en la cual distintos kernels, o unidades de ejecución, se ejecuten en un numero variable de aceleradores hardware sin necesidad de cambios en el código de aplicación. • Proponer un diseño y proporcionar una arquitectura en la que las condiciones de trabajo cambien de forma dinámica dependiendo bien de parámetros externos o bien de parámetros que indiquen el estado de la plataforma. Estos cambios en el punto de trabajo de la arquitectura serán posibles gracias a la reconfiguración dinámica y parcial de aceleradores hardware en tiempo real. • Explotar las posibilidades de procesamiento concurrente, incluso en una arquitectura basada en bus, por medio de la optimización de las transacciones en ráfaga de datos hacia los aceleradores. •Aprovechar las ventajas ofrecidas por la aceleración lograda por módulos puramente hardware para conseguir una mejor eficiencia energética. • Ser capaces de cambiar los niveles de redundancia de hardware de forma dinámica según las necesidades del sistema en tiempo real y sin cambios para el código de aplicación. • Proponer una capa de abstracción entre el código de aplicación y el uso dinámico de los recursos de la FPGA. El diseño en FPGAs permite la utilización de módulos hardware específicamente creados para una aplicación concreta. De esta forma es posible obtener rendimientos mucho mayores que en el caso de las arquitecturas de propósito general. Además, algunas FPGAs permiten la reconfiguración dinámica y parcial de ciertas partes de su lógica en tiempo de ejecución, lo cual dota al diseño de una gran flexibilidad. Los fabricantes de FPGAs ofrecen arquitecturas predefinidas con la posibilidad de añadir bloques prediseñados y poder formar sistemas en chip de una forma más o menos directa. Sin embargo, la forma en la que estos módulos hardware están organizados dentro de la arquitectura interna ya sea estática o dinámicamente, o la forma en la que la información se intercambia entre ellos, influye enormemente en la capacidad de cómputo y eficiencia energética del sistema. De la misma forma, la capacidad de cargar módulos hardware bajo demanda, permite añadir bloques redundantes que permitan aumentar el nivel de tolerancia a fallos de los sistemas. Sin embargo, la complejidad ligada al diseño de bloques hardware dedicados no debe ser subestimada. Es necesario tener en cuenta que el diseño de un bloque hardware no es sólo su propio diseño, sino también el diseño de sus interfaces, y en algunos casos de los drivers software para su manejo. Además, al añadir más bloques, el espacio de diseño se hace más complejo, y su programación más difícil. Aunque la mayoría de los fabricantes ofrecen interfaces predefinidas, IPs (por sus siglas en inglés, Intelectual Property) comerciales y plantillas para ayudar al diseño de los sistemas, para ser capaces de explotar las posibilidades reales del sistema, es necesario construir arquitecturas sobre las ya establecidas para facilitar el uso del paralelismo, la redundancia, y proporcionar un entorno que soporte la gestión dinámica de los recursos. Para proporcionar este tipo de soporte, ARTICo3 trabaja con un espacio de soluciones formado por tres ejes fundamentales: computación, consumo energético y confiabilidad. De esta forma, cada punto de trabajo se obtiene como una solución de compromiso entre estos tres parámetros. Mediante el uso de la reconfiguración dinámica y parcial y una mejora en la transmisión de los datos entre la memoria principal y los aceleradores, es posible dedicar un número variable de recursos en el tiempo para cada tarea, lo que hace que los recursos internos de la FPGA sean virtualmente ilimitados. Este variación en el tiempo del número de recursos por tarea se puede usar bien para incrementar el nivel de paralelismo, y por ende de aceleración, o bien para aumentar la redundancia, y por lo tanto el nivel de tolerancia a fallos. Al mismo tiempo, usar un numero óptimo de recursos para una tarea mejora el consumo energético ya que bien es posible disminuir la potencia instantánea consumida, o bien el tiempo de procesamiento. Con el objetivo de mantener los niveles de complejidad dentro de unos límites lógicos, es importante que los cambios realizados en el hardware sean totalmente transparentes para el código de aplicación. A este respecto, se incluyen distintos niveles de transparencia: • Transparencia a la escalabilidad: los recursos usados por una misma tarea pueden ser modificados sin que el código de aplicación sufra ningún cambio. • Transparencia al rendimiento: el sistema aumentara su rendimiento cuando la carga de trabajo aumente, sin cambios en el código de aplicación. • Transparencia a la replicación: es posible usar múltiples instancias de un mismo módulo bien para añadir redundancia o bien para incrementar la capacidad de procesamiento. Todo ello sin que el código de aplicación cambie. • Transparencia a la posición: la posición física de los módulos hardware es arbitraria para su direccionamiento desde el código de aplicación. • Transparencia a los fallos: si existe un fallo en un módulo hardware, gracias a la redundancia, el código de aplicación tomará directamente el resultado correcto. • Transparencia a la concurrencia: el hecho de que una tarea sea realizada por más o menos bloques es transparente para el código que la invoca. Por lo tanto, esta tesis doctoral contribuye en dos líneas diferentes. En primer lugar, con el diseño de la plataforma HiReCookie y en segundo lugar con el diseño de la arquitectura ARTICo3. Las principales contribuciones de esta tesis se resumen a continuación. • Arquitectura de la HiReCookie incluyendo: o Compatibilidad con la plataforma Cookies para incrementar las capacidades de esta. o División de la arquitectura en distintas islas de alimentación. o Implementación de los diversos modos de bajo consumo y políticas de despertado del nodo. o Creación de un archivo de configuración de la FPGA comprimido para reducir el tiempo y el consumo de la configuración inicial. • Diseño de la arquitectura reconfigurable para FPGAs basadas en RAM ARTICo3: o Modelo de computación y modos de ejecución inspirados en el modelo de CUDA pero basados en hardware reconfigurable con un número variable de bloques de hilos por cada unidad de ejecución. o Estructura para optimizar las transacciones de datos en ráfaga proporcionando datos en cascada o en paralelo a los distinto módulos incluyendo un proceso de votado por mayoría y operaciones de reducción. o Capa de abstracción entre el procesador principal que incluye el código de aplicación y los recursos asignados para las diferentes tareas. o Arquitectura de los módulos hardware reconfigurables para mantener la escalabilidad añadiendo una la interfaz para las nuevas funcionalidades con un simple acceso a una memoria RAM interna. o Caracterización online de las tareas para proporcionar información a un módulo de gestión de recursos para mejorar la operación en términos de energía y procesamiento cuando además se opera entre distintos nieles de tolerancia a fallos. El documento está dividido en dos partes principales formando un total de cinco capítulos. En primer lugar, después de motivar la necesidad de nuevas plataformas para cubrir las nuevas aplicaciones, se detalla el diseño de la plataforma HiReCookie, sus partes, las posibilidades para bajar el consumo energético y se muestran casos de uso de la plataforma así como pruebas de validación del diseño. La segunda parte del documento describe la arquitectura reconfigurable, su implementación en varias FPGAs, y pruebas de validación en términos de capacidad de procesamiento y consumo energético, incluyendo cómo estos aspectos se ven afectados por el nivel de tolerancia a fallos elegido. Los capítulos a lo largo del documento son los siguientes: El capítulo 1 analiza los principales objetivos, motivación y aspectos teóricos necesarios para seguir el resto del documento. El capítulo 2 está centrado en el diseño de la plataforma HiReCookie y sus posibilidades para disminuir el consumo de energía. El capítulo 3 describe la arquitectura reconfigurable ARTICo3. El capítulo 4 se centra en las pruebas de validación de la arquitectura usando la plataforma HiReCookie para la mayoría de los tests. Un ejemplo de aplicación es mostrado para analizar el funcionamiento de la arquitectura. El capítulo 5 concluye esta tesis doctoral comentando las conclusiones obtenidas, las contribuciones originales del trabajo y resultados y líneas futuras. ABSTRACT This PhD Thesis is framed within the field of dynamically reconfigurable embedded systems, advanced sensor networks and distributed computing. The document is centred on the study of processing solutions for high-performance autonomous distributed systems (HPADS) as well as their evolution towards High performance Computing (HPC) systems. The approach of the study is focused on both platform and processor levels to optimise critical aspects such as computing performance, energy efficiency and fault tolerance. HPADS are considered feedback systems, normally networked and/or distributed, with real-time adaptive and predictive functionality. These systems, as part of more complex systems known as Cyber-Physical Systems (CPSs), can be applied in a wide range of fields such as military, health care, manufacturing, aerospace, etc. For the design of HPADS, high levels of dependability, the definition of suitable models of computation, and the use of methodologies and tools to support scalability and complexity management, are required. The first part of the document studies the different possibilities at platform design level in the state of the art, together with description, development and validation tests of the platform proposed in this work to cope with the previously mentioned requirements. The main objectives targeted by this platform design are the following: • Study the feasibility of using SRAM-based FPGAs as the main processor of the platform in terms of energy consumption and performance for high demanding applications. • Analyse and propose energy management techniques to reduce energy consumption in every stage of the working profile of the platform. • Provide a solution with dynamic partial and wireless remote HW reconfiguration (DPR) to be able to change certain parts of the FPGA design at run time and on demand without interrupting the rest of the system. • Demonstrate the applicability of the platform in different test-bench applications. In order to select the best approach for the platform design in terms of processing alternatives, a study of the evolution of the state-of-the-art platforms is required to analyse how different architectures cope with new more demanding applications and scenarios: security, mixed-critical systems for aerospace, multimedia applications, or military environments, among others. In all these scenarios, important changes in the required processing bandwidth or the complexity of the algorithms used are provoking the migration of the platforms from single microprocessor architectures to multiprocessing and heterogeneous solutions with more instant power consumption but higher energy efficiency. Within these solutions, FPGAs and Systems on Chip including FPGA fabric and dedicated hard processors, offer a good trade of among flexibility, processing performance, energy consumption and price, when they are used in demanding applications where working conditions are very likely to vary over time and high complex algorithms are required. The platform architecture proposed in this PhD Thesis is called HiReCookie. It includes an SRAM-based FPGA as the main and only processing unit. The FPGA selected, the Xilinx Spartan-6 LX150, was at the beginning of this work the best choice in terms of amount of resources and power. Although, the power levels are the lowest of these kind of devices, they can be still very high for distributed systems that normally work powered by batteries. For that reason, it is necessary to include different energy saving possibilities to increase the usability of the platform. In order to reduce energy consumption, the platform architecture is divided into different power islands so that only those parts of the systems that are strictly needed are powered on, while the rest of the islands can be completely switched off. This allows a combination of different low power modes to decrease energy. In addition, one of the most important handicaps of SRAM-based FPGAs is that they are not alive at power up. Therefore, recovering the system from a switch-off state requires to reload the FPGA configuration from a non-volatile memory device. For that reason, this PhD Thesis also proposes a methodology to compress the FPGA configuration file in order to reduce time and energy during the initial configuration process. Although some of the requirements for the design of HPADS are already covered by the design of the HiReCookie platform, it is necessary to continue improving energy efficiency, computing performance and fault tolerance. This is only possible by exploiting all the opportunities provided by the processing architectures configured inside the FPGA. Therefore, the second part of the thesis details the design of the so called ARTICo3 FPGA architecture to enhance the already intrinsic capabilities of the FPGA. ARTICo3 is a DPR-capable bus-based virtual architecture for multiple HW acceleration in SRAM-based FPGAs. The architecture provides support for dynamic resource management in real time. In this way, by using DPR, it will be possible to change the levels of computing performance, energy consumption and fault tolerance on demand by increasing or decreasing the amount of resources used by the different tasks. Apart from the detailed design of the architecture and its implementation in different FPGA devices, different validation tests and comparisons are also shown. The main objectives targeted by this FPGA architecture are listed as follows: • Provide a method based on a multithread approach such as those offered by CUDA (Compute Unified Device Architecture) or OpenCL kernel executions, where kernels are executed in a variable number of HW accelerators without requiring application code changes. • Provide an architecture to dynamically adapt working points according to either self-measured or external parameters in terms of energy consumption, fault tolerance and computing performance. Taking advantage of DPR capabilities, the architecture must provide support for a dynamic use of resources in real time. • Exploit concurrent processing capabilities in a standard bus-based system by optimizing data transactions to and from HW accelerators. • Measure the advantage of HW acceleration as a technique to boost performance to improve processing times and save energy by reducing active times for distributed embedded systems. • Dynamically change the levels of HW redundancy to adapt fault tolerance in real time. • Provide HW abstraction from SW application design. FPGAs give the possibility of designing specific HW blocks for every required task to optimise performance while some of them include the possibility of including DPR. Apart from the possibilities provided by manufacturers, the way these HW modules are organised, addressed and multiplexed in area and time can improve computing performance and energy consumption. At the same time, fault tolerance and security techniques can also be dynamically included using DPR. However, the inherent complexity of designing new HW modules for every application is not negligible. It does not only consist of the HW description, but also the design of drivers and interfaces with the rest of the system, while the design space is widened and more complex to define and program. Even though the tools provided by the majority of manufacturers already include predefined bus interfaces, commercial IPs, and templates to ease application prototyping, it is necessary to improve these capabilities. By adding new architectures on top of them, it is possible to take advantage of parallelization and HW redundancy while providing a framework to ease the use of dynamic resource management. ARTICo3 works within a solution space where working points change at run time in a 3D space defined by three different axes: Computation, Consumption, and Fault Tolerance. Therefore, every working point is found as a trade-off solution among these three axes. By means of DPR, different accelerators can be multiplexed so that the amount of available resources for any application is virtually unlimited. Taking advantage of DPR capabilities and a novel way of transmitting data to the reconfigurable HW accelerators, it is possible to dedicate a dynamically-changing number of resources for a given task in order to either boost computing speed or adding HW redundancy and a voting process to increase fault-tolerance levels. At the same time, using an optimised amount of resources for a given task reduces energy consumption by reducing instant power or computing time. In order to keep level complexity under certain limits, it is important that HW changes are transparent for the application code. Therefore, different levels of transparency are targeted by the system: • Scalability transparency: a task must be able to expand its resources without changing the system structure or application algorithms. • Performance transparency: the system must reconfigure itself as load changes. • Replication transparency: multiple instances of the same task are loaded to increase reliability and performance. • Location transparency: resources are accessed with no knowledge of their location by the application code. • Failure transparency: task must be completed despite a failure in some components. • Concurrency transparency: different tasks will work in a concurrent way transparent to the application code. Therefore, as it can be seen, the Thesis is contributing in two different ways. First with the design of the HiReCookie platform and, second with the design of the ARTICo3 architecture. The main contributions of this PhD Thesis are then listed below: • Architecture of the HiReCookie platform including: o Compatibility of the processing layer for high performance applications with the Cookies Wireless Sensor Network platform for fast prototyping and implementation. o A division of the architecture in power islands. o All the different low-power modes. o The creation of the partial-initial bitstream together with the wake-up policies of the node. • The design of the reconfigurable architecture for SRAM FPGAs: ARTICo3: o A model of computation and execution modes inspired in CUDA but based on reconfigurable HW with a dynamic number of thread blocks per kernel. o A structure to optimise burst data transactions providing coalesced or parallel data to HW accelerators, parallel voting process and reduction operation. o The abstraction provided to the host processor with respect to the operation of the kernels in terms of the number of replicas, modes of operation, location in the reconfigurable area and addressing. o The architecture of the modules representing the thread blocks to make the system scalable by adding functional units only adding an access to a BRAM port. o The online characterization of the kernels to provide information to a scheduler or resource manager in terms of energy consumption and processing time when changing among different fault-tolerance levels, as well as if a kernel is expected to work in the memory-bounded or computing-bounded areas. The document of the Thesis is divided into two main parts with a total of five chapters. First, after motivating the need for new platforms to cover new more demanding applications, the design of the HiReCookie platform, its parts and several partial tests are detailed. The design of the platform alone does not cover all the needs of these applications. Therefore, the second part describes the architecture inside the FPGA, called ARTICo3, proposed in this PhD Thesis. The architecture and its implementation are tested in terms of energy consumption and computing performance showing different possibilities to improve fault tolerance and how this impact in energy and time of processing. Chapter 1 shows the main goals of this PhD Thesis and the technology background required to follow the rest of the document. Chapter 2 shows all the details about the design of the FPGA-based platform HiReCookie. Chapter 3 describes the ARTICo3 architecture. Chapter 4 is focused on the validation tests of the ARTICo3 architecture. An application for proof of concept is explained where typical kernels related to image processing and encryption algorithms are used. Further experimental analyses are performed using these kernels. Chapter 5 concludes the document analysing conclusions, comments about the contributions of the work, and some possible future lines for the work.