Certification and integration of management systems: the experience of Portuguese small and medium enterprises

The purpose of this study was to characterize the situation of Portuguese Small and Medium Enterprises (SMEs) concerning the certification of their Quality Management Systems (QMS), Environmental Management Systems (EMS) and Occupational Health and Safety Management Systems (OHSMS), in their individually form, to identify benefits, drawbacks and difficulties associated with the certification process and to characterize the level of integration that has been achieved. This research was based on a survey carried out by the research team; it was administered to 46 Portuguese SMEs. Our sample comprised 20 firms (43%) from the Trade/Services activity sector, 17 (37%) from the Industrial sector, 5 (11%) from the Electricity/Telecommunications sector and 4 (9%) from the Construction area. All SMEs surveyed were certified according to the ISO 9001 (100%), a quarter of firms were certified according to the ISO 14001 (26.1%) and a few certified by OHSAS 18001 (15.2%). We undertook a multivariate cluster analysis, which enabled grouping variables into homogeneous groups or one or more common characteristics of the SMEs participating in the study. Results show that the main benefits that Portuguese SMEs have gained from the referred certifications have been, among others, an improvement of both their internal organization and external image. We also present the main difficulties in achieving certification. Overall, 7 of the Portuguese SMEs examined indicated that the main benefits of the IMS implementation management included costs reduction, increased employee training and easier compliance of legislation. The respective drawbacks and difficulties are also presented. Finally, we presented the main integrated items in the certified Portuguese SMEs we examined.

Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.

Projecto de um conversor redutor CC-CC comutado para SoC

A evolução da tecnologia CMOS tem possibilitado uma maior densidade de integração de circuitos tornando possível o aumento da complexidade dos sistemas. No entanto, a integração de circuitos de gestão de potência continua ainda em estudo devido à dificuldade de integrar todos os componentes. Esta solução apresenta elevadas vantagens, especialmente em aplicações electrónicas portáteis alimentadas a baterias, onde a autonomia é das principais características. No âmbito dos conversores redutores existem várias topologias de circuitos que são estudadas na área de integração. Na categoria dos conversores lineares utiliza-se o LDO (Low Dropout Regulator), apresentando no entanto baixa eficiência para relações de conversão elevadas. Os conversores comutados são elaborados através do recurso a circuitos de comutação abrupta, em que a eficiência deste tipo de conversores não depende do rácio de transformação entre a tensão de entrada e a de saída. A diminuição física dos processos CMOS tem como consequência a redução da tensão máxima que os transístores suportam, impondo o estudo de soluções tolerantes a “altatensão”, com o intuito de manter compatibilidade com tensões superiores que existam na placa onde o circuito é incluído. Os sistemas de gestão de energia são os primeiros a acompanhar esta evolução, tendo de estar aptos a fornecer a tensão que os restantes circuitos requerem. Neste trabalho é abordada uma metodologia de projecto para conversores redutores CCCC comutados em tecnologia CMOS, tendo-se maximizado a frequência com vista à integração dos componentes de filtragem em circuito integrado. A metodologia incide sobre a optimização das perdas totais inerentes à comutação e condução, dos transístores de potência e respectivos circuitos auxiliares. É apresentada uma nova metodologia para o desenvolvimento de conversores tolerantes a “alta-tensão”.

Conectividade estrutural do cérebro

Mestrado em Radiações Aplicadas às Tecnologias da Saúde. Área de especialização: Ressonância Magnética

An efficient method for optimal location and sizing of fixed and switched shunt capacitors in large distribution systems

This paper proposes a computationally efficient methodology for the optimal location and sizing of static and switched shunt capacitors in large distribution systems. The problem is formulated as the maximization of the savings produced by the reduction in energy losses and the avoided costs due to investment deferral in the expansion of the network. The proposed method selects the nodes to be compensated, as well as the optimal capacitor ratings and their operational characteristics, i.e. fixed or switched. After an appropriate linearization, the optimization problem was formulated as a large-scale mixed-integer linear problem, suitable for being solved by means of a widespread commercial package. Results of the proposed optimizing method are compared with another recent methodology reported in the literature using two test cases: a 15-bus and a 33-bus distribution network. For the both cases tested, the proposed methodology delivers better solutions indicated by higher loss savings, which are achieved with lower amounts of capacitive compensation. The proposed method has also been applied for compensating to an actual large distribution network served by AES-Venezuela in the metropolitan area of Caracas. A convergence time of about 4 seconds after 22298 iterations demonstrates the ability of the proposed methodology for efficiently handling large-scale compensation problems.

A 5GHz1.8V Low Power CMOS Low-Noise Amplifier

Wireless local-area networks (WLANs) have been deployed as office and home communications infrastructures worldwide. The diversification of the standards, such as IEEE 802.11 series demands the design of RF front-ends. Low power consumption is one of the most important design concerns in the application of those technologies. To maintain competitive hardware costs, CMOS has been used since it is the best solution for low cost and high integration processing, allowing analog circuits to be mixed with digital ones. In the receiver chain, the low noise amplifier (LNA) is one of the most critical blocks in a transceiver design. The sensitivity is mainly determined by the LNA noise figure and gain. It interfaces with the pre-select filter and the mixer. Furthermore, since it is the first gain stage, care must be taken to provide accurate input match, low-noise figure, good linearity and a sufficient gain over a wide band of operation. Several CMOS LNAs have been reported during the last decade, showing that the most research has been done at 802.11/b and GSM standards (900-2400MHz spectrum) and more recently at 802.11/a (5GHz band). One of the more significant disadvantages of 802.11/b is that the frequency band is crowded and subject to interference from other technologies, as is 2.4GHz cordless phones and Bluetooth. As the demand for radio-frequency integrated circuits, operating at higher frequency bands, increases, the IEEE 802.11/a standard becomes a very attractive option to wireless communication system developers. This paper presents the design and implementation of a low power, low noise amplifier aimed at IEEE 802.11a for WLAN applications. It was designed to be integrated with an active balun and mixer, representing the first step toward a fully integrated monolithic WLAN receiver. All the required circuits are integrated at the same die and are powered by 1.8V supply source. Preliminary experimental results (S-parameters) are shown and promise excellent results. The LNA circuit design details are illustrated in Section 2. Spectre simulation results focused at gain, noise figure (NF) and input/output matching are presented in Section 3. Finally, conclusions and comparison with other recently reported LNAs are made in Section 4, followed by future work.

Conectividade estrutural do cérebro: diferenças entre um cérebro normal e um cérebro com patologia

Perceber a rede estrutural formada pelos neurónios no cérebro a nível da macro escala é um desafio atual na área das neurociências. Neste estudo analisou-se a conectividade estrutural do cérebro em 22 indivíduos saudáveis e em dois doentes com epilepsia pós-traumática. Avaliaram-se as diferenças entre estes dois grupos. Também se pesquisaram diferenças a nível do género e idade no grupo de indivíduos saudáveis e os que têm valores médios mais elevados nas métricas de caracterização da rede. Para tal, desenvolveu-se um protocolo de análise recorrendo a diversos softwares especializados e usaram-se métricas da Teoria dos Grafos para a caracterização da conectividade estrutural entre 118 regiões encefálicas distintas. Dentro do grupo dos indivíduos saudáveis concluiu-se que os homens, no geral, são os que têm média mais alta para as métricas de caracterização da rede estrutural. Contudo, não se observaram diferenças significativas em relação ao género nas métricas de caracterização global do cérebro. Relativamente à idade, esta correlaciona-se negativamente, no geral, com as métricas de caracterização da rede estrutural. As regiões onde se observaram as diferenças mais importantes entre indivíduos saudáveis e doentes são: o sulco rolândico, o hipocampo, o pré-cuneus, o tálamo e o cerebelo bilateralmente. Estas diferenças são consistentes com as imagens radiológicas dos doentes e com a literatura estudada sobre a epilepsia pós-traumática. Preveem-se desenvolvimentos para o estudo da conectividade estrutural do cérebro humano, uma vez que a sua potencialidade pode ser combinada com outros métodos de modo a caracterizar as alterações dos circuitos cerebrais.

A vision of cyber-physical internet

When the Internet was born, the purpose was to interconnect computers to share digital data at large-scale. On the other hand, when embedded systems were born, the objective was to control system components under real-time constraints through sensing devices, typically at small to medium scales. With the great evolution of the Information and Communication Technology (ICT), the tendency is to enable ubiquitous and pervasive computing to control everything (physical processes and physical objects) anytime and at a large-scale. This new vision gave recently rise to the paradigm of Cyber-Physical Systems (CPS). In this position paper, we provide a realistic vision to the concept of the Cyber-Physical Internet (CPI), discuss its design requirements and present the limitations of the current networking abstractions to fulfill these requirements. We also debate whether it is more productive to adopt a system integration approach or a radical design approach for building large-scale CPS. Finally, we present a sample of realtime challenges that must be considered in the design of the Cyber-Physical Internet.

A CMOS micro power switched-capacitor DC-DC step-up converter for indoor light energy harvesting applications

This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V-OC) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm(2) in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm(2), is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m(2). After starting-up, the system requires an irradiance of only 0.18 W/m(2) (18 mu W/cm(2)) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 mu W. These values are, to the best of the authors' knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 mu W, which is comparable with reported values from circuits operating at similar power levels.

Novel techniques for the design and practical realization of switched-capacitor circuits in deep-submicron CMOS technologies

Dissertação apresentada para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores pela Universidade Nova de Lisboa, Faculdade de Ciências e Tecnologia

Impacto da introdução de baterias num SEE isolado: o caso da ilha da Madeira

Com a crescente integração de energias renováveis variáveis nos sistemas elétricos de energia surgem novos desafios à maneira como se efetua a exploração dos mesmos, devido à dificuldade na previsão produção e na controlabilidade destas energias. Estes desafios são ainda maiores quando se analisa uma rede elétrica isolada de pequenas dimensões sem possibilidade de ser interligada a uma rede continental, por apresentar uma maior fragilidade e dai resultarem critérios de exploração muito mais apertados, de forma a garantir da melhor forma a segurança e estabilidade da rede. Consequentemente existe a necessidade de serem adotadas medidas que atenuem os impactos da variabilidade e tornem mais previsíveis as energias renováveis. É neste âmbito que surgem as tecnologias de armazenamento de energia elétrica. O presente documento apresenta um estudo aprofundado ao sistema eletroprodutor da ilha da Madeira e às suas especificidades, analisando a viabilidade técnica da introdução de baterias em larga escala no sistema. De forma a realizar esta análise, criou-se uma ferramenta de simulação em Matlab, que visou quantificar o impacto da introdução de baterias, quer ao nível da integração de energia eólica, quer ao nível da redução da produção térmica. Esta ferramenta permite ainda uma análise gráfica do diagrama de produção agregado diário, assim como a evolução de potência e energia na bateria.

A multiplying-by-two CMOS amplifier for high-speed ADCs based on parametric amplification

15th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 177 – 180, Poznan, Polónia

Scale-free networks and scalable interdomain routing

Trabalho apresentado no âmbito do Mestrado em Engenharia Informática, como requisito parcial para obtenção do grau de Mestre em Engenharia Informática

Simple and stable dynamic traffic engineering for provider scale ethernet

Trabalho apresentado no âmbito do Mestrado em Engenharia Informática, como requisito parcial para obtenção do grau de Mestre em Engenharia Informática

Automated image tagging through tag propagation

Trabalho apresentado no âmbito do Mestrado em Engenharia Informática, como requisito parcial Para obtenção do grau de Mestre em Engenharia Informática