Les étudiant(e)s en médecine mènent une recherche dans La communauté [Male/female medical students conduct research in the community].

Pendant quatre semaines, les étudiant(e)s en médecine de 3e année de l'Université de Lausanne mènent une enquête dans la communauté sur le sujet de leur choix. L'objectif de ce module est de faire découvrir aux futurs médecins les déterminants non biomédicaux de la santé, de la maladie et de l'exercice de la médecine : les styles de vie, les facteurs psychosociaux et culturels, l'environnement, les décisions politiques, les contraintes économiques, les questions éthiques, etc. Par groupes de cinq, les étudiant(e)s commencent par définir une question de recherche originale et en explorent la littérature scientifique. Leur travail de recherche les amène à entrer en contact avec le réseau d'acteurs de la communauté concernés, professionnels ou associations de patients dont ils analysent les rôles et influences respectives. Chaque groupe est accompagné par un(e) tuteur(trice), enseignant(e) de la Faculté de biologie et de médecine de l'Université de Lausanne. Les étudiant(e)s présentent la synthèse de leurs travaux pendant un congrès de deux jours à la fin du module. Quatre travaux parmi les plus remarquables ont été choisis pour être publiés dans la Revue Médicale Suisse et Primary Care.

Comparative dosimetry in intracavitary balloon catheter brachytherapy with I-125 and in Cf-252 brachytherapy combined with BNCT for brain tumors

Objective Comparative analysis of dosimetry in intracavitary balloon catheter brachytherapy with I-125 and in Cf-252 brachytherapy combined with BNCT for treatment of brain tumors. Materials and Methods Simulations of intracavitary balloon catheter brachytherapy with I-125 and in Cf-252 brachytherapy combined with BNCT were performed with the MCNP5 code, modeling the treatment of a brain tumor on a voxel computational phantom representing a human head. Absorbed dose rates were converted into biologically weighted dose rates. Results Intracavitary balloon catheter brachytherapy with I-125 produced biologically weighted mean dose rates of 3.2E-11, 1.3E-10, 1.9E-11 and 6.9E-13 RBE.Gy.h-1.p-1.s, respectively, on the healthy tissue, on the balloon periphery and on the I 1 and I 2 tumor infiltration zones. On the other hand, Cf-252 brachytherapy combined with BNCT produced a biologically weighted mean dose rate of 5.2E-09, 2.3E-07, 8.7E-09 and 2.4E-09 RBE.Gy.h-1.p-1.s, respectively on the healthy tissue, on the target tumor and on the I 1 and I 2 infiltration zones. Conclusion Cf-252 brachytherapy combined with BNCT delivered a selective irradiation to the target tumor and to infiltration zones, while intracavitary balloon catheter brachytherapy with I-125 delivered negligible doses on the tumor infiltration zones.

A Co-Processor Approach for Efficient Java Execution in Embedded Systems

This thesis deals with a hardware accelerated Java virtual machine, named REALJava. The REALJava virtual machine is targeted for resource constrained embedded systems. The goal is to attain increased computational performance with reduced power consumption. While these objectives are often seen as trade-offs, in this context both of them can be attained simultaneously by using dedicated hardware. The target level of the computational performance of the REALJava virtual machine is initially set to be as fast as the currently available full custom ASIC Java processors. As a secondary goal all of the components of the virtual machine are designed so that the resulting system can be scaled to support multiple co-processor cores. The virtual machine is designed using the hardware/software co-design paradigm. The partitioning between the two domains is flexible, allowing customizations to the resulting system, for instance the floating point support can be omitted from the hardware in order to decrease the size of the co-processor core. The communication between the hardware and the software domains is encapsulated into modules. This allows the REALJava virtual machine to be easily integrated into any system, simply by redesigning the communication modules. Besides the virtual machine and the related co-processor architecture, several performance enhancing techniques are presented. These include techniques related to instruction folding, stack handling, method invocation, constant loading and control in time domain. The REALJava virtual machine is prototyped using three different FPGA platforms. The original pipeline structure is modified to suit the FPGA environment. The performance of the resulting Java virtual machine is evaluated against existing Java solutions in the embedded systems field. The results show that the goals are attained, both in terms of computational performance and power consumption. Especially the computational performance is evaluated thoroughly, and the results show that the REALJava is more than twice as fast as the fastest full custom ASIC Java processor. In addition to standard Java virtual machine benchmarks, several new Java applications are designed to both verify the results and broaden the spectrum of the tests.

Cosmos (1852)

Etat de collection : 3e s., t. 1 (1867, oct.-déc.) ; t. 3 (1868, juil.-déc.) ; t. 5 (1869, juil.-déc.) ; t. 7 (1870, juil.-août)

Étudiants et lorettes : almanach du quartier latin

Périodicité : Annuel

Kestomagneettitahtikoneen emulointi digitaalisella signaaliprosessorilla

Sähkökäytön suunnittelussa säätöä voidaan testata useassa tapauksessa reaaliaikasimulaattorilla todellisen laitteiston sijaan. Monet reaaliaikasimulaatioiden perustana käytetyt algoritmit soveltuvat täysinohjatulle invertterisillalle. Eräissä sovelluksissa halutaan kuitenkin käyttää puoliksiohjattua siltaa. Puoliksiohjattulla sillalla mallin kausaalisuus voi kääntyä, mitä perinteiset reaaliaikasimulaattorit eivät pysty simuloimaan Tässä työssä oli tavoitteena kehittää reaaliaikasimulaattori puoliksiohjatulle kestomagneettitahtikonekäytölle. Emulaattoriin mallinnettiin todellisen käytön kestomagneettitahtikone ja invertterisilta. Simulaattori toteutettiin digitaaliselle signaaliprosessorille (DSP) ja mittauksiin liittyvät oheislaitteet mallinnettiin FPGA-piirille. Emulaattoriin liitettiin erillinen säätäjä, jota käytettiin myös todellisen sähkökäytön säätämiseen. Emulaattorilla ja todellisella käytöllä tehtyjä mittauksia verrattiin ja emuloimalla saadut tulokset vastasivat melko hyvin todellisesta käytöstä mitattuja.

Field-Programmable Gate Array Card for Readout and Control of Cryoelectronics

The main goal of the present Master’s Thesis project was to create a field-programmable gate array (FPGA) based system for the control of single-electron transistors or other cryoelectronic devices. The FPGA and similar technologies are studied in the present work. The fixed and programmable logic are compared with each other. The main features and limitations of the hardware used in the project are investigated. The hardware and software connections of the device to the computer are shown in detail. The software development techniques for FPGA-based design are described. The steps of design for programmable logic are considered. Furthermore, the results of filters implemented in the software are illustrated.

One chip solution for low-cost active magnetic bearing system

In this work the implementation of the active magnetic bearing control system in a single FPGA is studied. Requirements for the full magnetic bearing control system are reviewed. Different control methods for active magnetic bearings are described shortly. Flux and the current base controllers are implemented in a FPGA. Suitability of the con-trollers for a low-cost magnetic bearing application is studied. Floating-point arithmetic’s are used in the controllers to ease designing burden and improve calculation precision. Per-formance of the flux controller is verified with simulations.

Invenio customization for CERN Document Server

Presentation at Open Repositories 2014, Helsinki, Finland, June 9-13, 2014

The CERN Multimedia Repository

Presentation at Open Repositories 2014, Helsinki, Finland, June 9-13, 2014

Integration of JINR Information Resources

Presentation at Open Repositories 2014, Helsinki, Finland, June 9-13, 2014

Study of Control Methods of a High-Frequency Cycloconverter for Domestic Induction Heating Appliances

A high-frequency cyclonverter acts as a direct ac-to-ac power converter circuit that does not require a diode bidge rectifier. Bridgeless topology makes it possible to remove forward voltage drop losses that are present in a diode bridge. In addition, the on-state losses can be reduced to 1.5 times the on-state resistance of switches in half-bridge operation of the cycloconverter. A high-frequency cycloconverter is reviewed and the charging effect of the dc-capacitors in ``back-to-back'' or synchronous mode operation operation is analyzed. In addition, a control method is introduced for regulating dc-voltage of the ac-side capacitors in synchronous operation mode. The controller regulates the dc-capacitors and prevents switches from reaching overvoltage level. This can be accomplished by variating phase-shift between the upper and the lower gate signals. By adding phase-shift between the gate signal pairs, the charge stored in the energy storage capacitors can be discharged through the resonant load and substantially, the output resonant current amplitude can be improved. The above goals are analyzed and illustrated with simulation. Theory is supported with practical measurements where the proposed control method is implemented in an FPGA device and tested with a high-frequency cycloconverter using super-junction power MOSFETs as switching devices.

Chronicon episcoporum Finlandensium 26

Painovuosi nimekkeestä.

Power and Performance Management Strategies on NoC-Based Multicore Platforms, Using DVFS, Adaptive Algorithm and Task Parallelism

This work presents synopsis of efficient strategies used in power managements for achieving the most economical power and energy consumption in multicore systems, FPGA and NoC Platforms. In this work, a practical approach was taken, in an effort to validate the significance of the proposed Adaptive Power Management Algorithm (APMA), proposed for system developed, for this thesis project. This system comprise arithmetic and logic unit, up and down counters, adder, state machine and multiplexer. The essence of carrying this project firstly, is to develop a system that will be used for this power management project. Secondly, to perform area and power synopsis of the system on these various scalable technology platforms, UMC 90nm nanotechnology 1.2v, UMC 90nm nanotechnology 1.32v and UMC 0.18 μmNanotechnology 1.80v, in order to examine the difference in area and power consumption of the system on the platforms. Thirdly, to explore various strategies that can be used to reducing system’s power consumption and to propose an adaptive power management algorithm that can be used to reduce the power consumption of the system. The strategies introduced in this work comprise Dynamic Voltage Frequency Scaling (DVFS) and task parallelism. After the system development, it was run on FPGA board, basically NoC Platforms and on these various technology platforms UMC 90nm nanotechnology1.2v, UMC 90nm nanotechnology 1.32v and UMC180 nm nanotechnology 1.80v, the system synthesis was successfully accomplished, the simulated result analysis shows that the system meets all functional requirements, the power consumption and the area utilization were recorded and analyzed in chapter 7 of this work. This work extensively reviewed various strategies for managing power consumption which were quantitative research works by many researchers and companies, it's a mixture of study analysis and experimented lab works, it condensed and presents the whole basic concepts of power management strategy from quality technical papers.

Mémorial topographique et militaire, rédigé au Dépôt général de la guerre : imprimé par ordre du ministre

Variante(s) de titre : Mémoire sur la projection des cartes géographiques, adoptée au Dépôt général de la Guerre