An accurate low-voltage analog memory-cell with built-in multiplication

A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gain-boosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transconductor and the stored voltage is provided. Designing complies with a low-voltage 1.2μm N-well CMOS fabrication process. For a 1.3V-supply, CCELL=3.6pF and sampling interval is 0.25μA≤ ISAMPLE ≤ 0.75μA. The specified retention time is 1.28ms and corresponds to a charge-variation of 1% due to junction leakage @75°C. A range of MR simulations confirm circuit performance. Absolute read-out error is below O.40% while the four-quadrant multiplier nonlinearity, at full-scale is 8.2%. Maximum stand-by consumption is 3.6μW/cell.

A low-voltage triode-MOSFET four-quadrant multiplier with optimized current-efficiency

A low-voltage, low-power four-quadrant analog multiplier with optimized current-efficiency is presented. Its core corresponds to a pseudodifferential cascode, gain-boosting triode-transconductor. According to a low-voltage 1.2μm CMOS n-well process, operand differential-amplitudes are 1.0Vpp and 0.32Vpp for a 1.3V-supply. Common-mode voltages are properly chosen to maximize current-efficiency to 58%. Total quiescent dissipation is 260μW. A range of PSPICE simulation supports theoretical analysis. Excellent linearity is observed on dc characteristic. Assuming a ±0.5% mismatch on (W/L) and VTH THD at full-scale is 0.93% and 1.42%, for output frequencies of 1MHz and 10MHz, respectively.

Effect of powder milling and dopant addition on the current-voltage characteristics of SnO2-based ceramics

Non-linear electrical properties of SnO2-based ceramics were investigated as a function of powder agglomeration condition and as a function of dopant addition. All doped powders presented a single phase, cassiterite, as evidenced by X-ray diffraction analysis. The effect of milling was quite evident, with non-milled powder showing higher agglomerated particle size than milled powder. Cr addition seemed to increase the non-linear coefficient. Cu and Mn rendered dense ceramics, but α values for systems with Mn were higher than for systems with Cu.

A new solution to the optimal power flow problem

A new approach to solving the Optimal Power Flow problem is described, making use of some recent findings, especially in the area of primal-dual methods for complex programming. In this approach, equality constraints are handled by Newton's method inequality constraints for voltage and transformer taps by the logarithmic barrier method and the other inequality constraints by the augmented Lagrangian method. Numerical test results are presented, showing the effective performance of this algorithm. © 2001 IEEE.

A high efficiency HPF-ZCS-PWM Sepic for electronic ballast with multiple tubular fluorescent lamps

This paper presents a high efficiency Sepic rectifier for an electronic ballast application with multiple fluorescent lamps. The proposed Sepic rectifier is based on a Zero-Current-Switching (ZCS) Pulse-Width-Modulated (PWM) soft-commutation cell. The high power-factor of this structure is obtained using the instantaneous average-current control technique, in order to attend properly IEC61000-3-2 standards. The inverting stage of this new electronic ballast is a classical Zero-Voltage-Switching (ZVS) Half-Bridge inverter. A proper design methodology is developed for this new electronic ballast, and a design example is presented for an application with five fluorescent lamps 40W-T12 (200W output power), 220Vrms input voltage, 130Vdc dc link voltage, with rectifier and inverter stages operating at 50kHz. Experimental results are also presented. The THD at input current is equal to 6.41%, for an input voltage THD equal to 2.14%, and the measured overall efficiency is about 92.8%, at rated load.

Electrode poling of cellular polypropylene films with short high-voltage pulses

Recently, piezoelectric cellular polypropylene (PP) was proposed as a new type of quasi-ferroelectric. The observed hysteresis of the charge density as a function of the electric field could be explained as field-dependent charging inside the gas-filled voids. Interestingly enough, the measurable poling behavior of the macroscopic dipoles formed by charges that are trapped at the internal void surfaces is phenomenologically completely identical to the cooperative poling behavior of microscopic molecular dipoles in ferroelectric polymers. Therefore, it can be assumed that charge separation (or charge redistribution) and subsequent trapping in cellular PP is a rather fast switching process. In order to examine the poling dynamics, we developed an experimental setup for pulsed poling. High-voltage pulses with a duration of 45 μs (FWHM) were applied in direct contact to two-side metallized cellular PP films. The pulsed poling yields piezoelectricity in the cellular PP. We study and discuss the dependence of the resulting piezoelectricity on the poling field. We also characterize the charge separation during application of higher electric poling fields of up to -10 kV in direct contact to the two-side metallized films for longer times.

A linearly-tunable OTA-C sinusoidal oscillator for low-voltage applications

A low-voltage, low-power OTA-C sinusoidal oscillator based on a triode-MOSFET transconductor is here discussed. The classical quadrature model is employed and the transconductor inherent nonlinear characteristic with input voltage is used as the amplitude-stabilization element. An external bias VTUNE linearly adjusts the oscillation frequency. According to a standard 0.8μm CMOS n-well process, a prototype was integrated, with an effective area of 0.28mm2. Experimental data validate the theoretical analysis. For a single 1.8V-supply and 100mV≤VTUNE≤250mV, the oscillation frequency fo ranges from 0.50MHz to 1.125MHz, with a nearly constant gain KVCO=4.16KHz/mV. Maximum output amplitude is 374mVpp @1.12MHz. THD is -41dB @321mVpp. Maximum average consumption is 355μW.

Identification of synchronous machine parameters using load rejection test data

This work shows a computational methodology for the determination of synchronous machines parameters using load rejection test data. By machine modeling one can obtain the quadrature parameters through a load rejection under an arbitrary reference, reducing the present difficulties. The proposed method is applied to a real machine.

A low-voltage programmable-gain current-mode amplifier

A CMOS low-voltage, wide-band continuous-time current amplifier is presented. Based on an open-loop topology, the circuit is composed by transresistance and transconductance stages built around triode-operating transistors. In addition to an extended dynamic range, the amplifier gain can be programmed within good accuracy by the rapport between the aspect-ratio of such transistors and tuning biases Vxand Vy. A balanced current-amplifier according to a single I. IV-supply and a 0.35μm fabrication process is designed. Simulated results from PSPiCE and Bsm3v3 models indicate a programmable gain within the range 20-34dB and a minimum break-frequency of IMHz @CL=IpF. For a 200 μApp-level, THD is 0.8% and 0.9% at IKHz and 100KHz, respectively. Input noise is 405pA√Hz @20dB-gain, which gives a SNR of 66dB @1MHz-bandwidth. Maximum quiescent power consumption is 56μ W. © 2002 IEEE.

Stable and metastable ferroelectric polarization analyzed by the ramp voltage technique

The study of the stable and the metastable ferroelectric polarization of poly(vinylidene fluoride), PVDF, was performed using two successive equal sign ramp voltages, mediated by a short-circuit period. Rates from 10 V/s up to 0.7 MV/s were used. Results showed that they follow different formation kinetics; that the stable part decreases for higher ramp voltage rates and its apparent coercive field increases.

Using artificial intelligence for the control of medium voltage substations

This paper introduces a method for the supervision and control of devices in electric substations using fuzzy logic and artificial neural networks. An automatic knowledge acquisition process is included which allows the on-line processing of operator actions and the extraction of control rules to replace gradually the human operator. Some experimental results obtained by the application of the implemented software in a simulated environment with random signal generators are presented.

An active leakage-injection scheme applied to low-voltage SRAMs

An active leakage-injection scheme (ALIS) for low-voltage (LV) high-density (HD) SRAMs is presented. By means of a feedback loop comprising a servo-amplifier and a common-drain MOSFET, a current matching the respective bit-line leakage is injected onto the line during precharge and sensing, preventing the respective capacitances from erroneous discharges. The technique is able to handle leakages up to hundreds of μA at high operating temperatures. Since no additional timing is required, read-out operations are performed at no speed penalty. A simplified 256×1bit array was designed in accordance with a 0.35 CMOS process and 1.2V-supply. A range of PSPICE simulation attests the efficacy of ALIS. With an extra power consumption of 242 μW, a 200 μA-leakage @125°C, corresponding to 13.6 times the cell current, is compensated.

A fast electric load forecasting using adaptive neural networks

This work presents a procedure for electric load forecasting based on adaptive multilayer feedforward neural networks trained by the Backpropagation algorithm. The neural network architecture is formulated by two parameters, the scaling and translation of the postsynaptic functions at each node, and the use of the gradient-descendent method for the adjustment in an iterative way. Besides, the neural network also uses an adaptive process based on fuzzy logic to adjust the network training rate. This methodology provides an efficient modification of the neural network that results in faster convergence and more precise results, in comparison to the conventional formulation Backpropagation algorithm. The adapting of the training rate is effectuated using the information of the global error and global error variation. After finishing the training, the neural network is capable to forecast the electric load of 24 hours ahead. To illustrate the proposed methodology it is used data from a Brazilian Electric Company. © 2003 IEEE.

A low-voltage low-sensitivity sinusoidal VCO for DPLL realizations

A quasi-sinusoidal linearly tunable OTA-C VCO built with triode-region transconductors is presented. Oscillation upon power-on is ensured by RHP poles associated with gate-drain capacitances of OTA input devices. Since the OTA nonlinearity stabilizes the amplitude, the oscillation frequency f0 is first-order independent of VDD, making the VCO adequate to mixed-mode designs. A range of simulations attests the theoretical analysis. As part of a DPLL, the VCO was prototyped on a 0.8μm CMOS process, occupying an area of 0.15mm2. Nominal f0 is 1MHz, with K VCo=8.4KHz/mV. Measured sensitivity to VDD is below 2.17, while phase noise is -86dBc at 100-KHz offset. The feasibility of the VCO for higher frequencies is verified by a redesign based on a 0.35μm CMOS process and VDD=3.3V, with a linear frequency-span of l3.2MHz - 61.5MHz.

A Gm-C bump equalizer for low-voltage low-power applications

A low-voltage low-power 2nd-order CMOS pseudo-differential bump-equalizer is presented. Its topology comprises a bandpass section with adjustable center frequency and quality factor, together with a programmable current amplifier. The basic building blocks are triode-operating transconductors, tunable by means of either a DC voltage or a digitally controlled current divider. The bump-equalizer as part of a battery-operated hearing aid device is designed for a 1.4V-supply and a 0.35μm CMOS fabrication process. The circuit performance is supported by a set of simulation results, which indicates a center frequency from 600Hz to 2.4kHz, 1≤Q≤5, and an adjustable gain within ±6dB at center frequency. The filter dynamic range lies around 40dB. Quiescent consumption is kept below 12μW for any configuration of the filter.