825 resultados para Fault Tolerance
Resumo:
Students referred to treatment after violating campus drug policies represent a high-risk group. Identification of factors related to these students’ cannabis use could inform prevention and treatment efforts. Distress tolerance (DT) is negatively related to substance-related behaviors and may be related to high-risk cannabis use vulnerability factors that can impact treatment outcome. Thus, the current study tested whether DT was related to cannabis use frequency, cannabis-related problems, and motivation to change cannabis use among 88 students referred for treatment after violating campus cannabis policies. DT was robustly, negatively related to cannabis use and related problems. DT was also significantly, negatively correlated with coping, conformity, and expansion motives. DT was directly and indirectly related to cannabis problems via coping (not conformity or expansion) motives. Motives did not mediate the relation of DT to cannabis use frequency. DT may be an important target in treatment with students who violate campus cannabis policies.
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This paper presents the application of the on-load exciting current Extended Park's Vector Approach for diagnosing incipient turn-to-turn winding faults in operating power transformers. Experimental and simulated test results demonstrate the effectiveness of the proposed technique, which is based on the spectral analysis of the AC component of the on-load exciting current Park's Vector modulus.
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One-year-old carob (Ceratonia siliqua L.) rootstock was grown in fertilised substrate to evaluate the effects of NaCl salinity stress. The experiment consisted of seven treatments with different concentrations of NaCl in the irrigation water: 0 (control), 15, 30, 40, 80, 120 and 240 (mmol L(-1)), equivalent to electrical conductivities of 0.0, 1.5, 2.9, 3.9, 7.5, 10.9 and 20.6 dS m(-1), respectively. Several growth parameters were measured throughout the experimental period. At the end of the experiment, pH, extractable P and K, and the electrical conductivity of the substrate were assessed in each salinity level. On the same date, the mineral composition of the leaves was compared. The carob rootstock tolerated 13.4 dS m(-1) for a period of 30 days but after 60 days the limit of tolerance was only 6.8 dS m(-1). Salt tolerance indexes were 12.8 and 4.5 for 30 and 60 days, respectively. This tolerance to salinity resulted from the ability to function with concentrations of Cl(-) and Na(+) in leaves up to 24.0 and 8.5 g kg(-1), respectively. Biomass allocation to shoots and roots was similar in all treatments, but after 40 days the number of leaves was reduced, particularly at the larger concentrations (120 and 240 mmol NaCl L(-1)). Leaves of plants irrigated with 240 mmol NaCl L(-1) became chlorotic after 30 days exposure. However, concentrations of N, P. Mg and Zn in leaves were not affected significantly (P > 0.05) by salinity. Apparently, K(+) and Ca(2+) were the key nutrients affected in the response of carob rootstocks to salinity. Plants grown with 80 and 120 mmol L(-1) of NaCl contained the greatest K. concentration. Na(+)/K(+) increased with salinity, due to an elevated Na(+) content but K(+) uptake was also enhanced, which alleviated some Na. stress. Ca(2+) concentration in leaves was not reduced under salinity. Salinization of irrigation water and subsequent impacts on agricultural soils are now common problems in the Mediterranean region. Under such conditions, carob seems to be a salt as well as a drought tolerant species. (C) 2010 Elsevier B.V. All rights reserved.
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On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.
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Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements
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The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.
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To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.
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Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.
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T lymphocytes reactive with the product of the Mlsa-allele of the minor lymphocyte stimulating (Mls) locus use a predominant T-cell receptor beta-chain variable gene segment (V beta 6). Such V beta 6-bearing T cells are selectively eliminated in the thymus of Mlsa-bearing mice, consistent with a model in which tolerance to self antigens is achieved by clonal deletion.
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The mechanisms by which CD4(+)CD25(+)Foxp3(+) T (Treg) cells regulate effector T cells in a transplantation setting and their in vivo homeostasis still remain to be clarified. Using a mouse adoptive transfer model, we analyzed the in vivo expansion, trafficking, and effector function of alloreactive T cells and donor-specific Treg cells, in response to a full-thickness skin allograft. Fluorescent-labeled CD4(+)CD25(-) and antigen-specific Treg cells were transferred alone or co-injected into syngeneic BALB/c-Nude recipients transplanted with skins from (C57BL/6 x BALB/c) F1 donors. Treg cells divided in vivo, migrated and accumulated in the allograft draining lymph nodes as well as within the graft. The co-transfer of Treg cells did not modify the early activation and homing of CD4(+)CD25(-) T cells in secondary lymphoid organs. However, in the presence of Treg cells, alloreactive CD4(+)CD25(-) T cells produced significantly less IFN-gamma and were present in reduced numbers in the secondary lymphoid organs. Furthermore, time-course studies showed that Treg cells were recruited into the allograft at a very early stage after transplantation and effectively prevented the infiltration of effector T cells. In conclusion, suppression of rejection requires the early recruitment to the site of antigenic challenge of donor-specific Treg cells, which then mainly regulate the effector arm of T cell alloresponses.
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Tesis (Doctor en Ingeniería Eléctrica) UANL, 2013.
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The study deals with the generation of variability for salt tolerance in rice using tissue culture techniques. Rice is the staple food of more than half of the world’s population. The management of drought, salinity and acidity in soils are all energy intensive agricultural practices. The Genetic variability is the basis of crop improvement. Somaclonal and androclonal variation can be effectively used for this purpose. In the present study, eight isozymes were studied and esterase and isocitric dehydrogenase was found to have varietal specific, developmental stage specific and stress specific banding pattern in rice. Under salt stress thickness of bands and enzyme activity showed changes. Pokkali, a moderately salt tolerant variety, had a specific band 7, which was present only in this variety and showed slight changes under stress. This band was faint in tillering and flowering stage .Based on the results obtained in the present study it is suggested that esterase could possibly be used as an isozyme marker for salt tolerance in rice. Varietal differences and stage specific variations could be detected using esterase and isocitric dehydrogenase . Moreover somaclonal and androclonal variation could be effectively detected using isozyme markers.
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The present research problem is to study the existing encryption methods and to develop a new technique which is performance wise superior to other existing techniques and at the same time can be very well incorporated in the communication channels of Fault Tolerant Hard Real time systems along with existing Error Checking / Error Correcting codes, so that the intention of eaves dropping can be defeated. There are many encryption methods available now. Each method has got it's own merits and demerits. Similarly, many crypt analysis techniques which adversaries use are also available.