919 resultados para Adaptive systems


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This paper discusses the monitoring of complex nonlinear and time-varying processes. Kernel principal component analysis (KPCA) has gained significant attention as a monitoring tool for nonlinear systems in recent years but relies on a fixed model that cannot be employed for time-varying systems. The contribution of this article is the development of a numerically efficient and memory saving moving window KPCA (MWKPCA) monitoring approach. The proposed technique incorporates an up- and downdating procedure to adapt (i) the data mean and covariance matrix in the feature space and (ii) approximates the eigenvalues and eigenvectors of the Gram matrix. The article shows that the proposed MWKPCA algorithm has a computation complexity of O(N2), whilst batch techniques, e.g. the Lanczos method, are of O(N3). Including the adaptation of the number of retained components and an l-step ahead application of the MWKPCA monitoring model, the paper finally demonstrates the utility of the proposed technique using a simulated nonlinear time-varying system and recorded data from an industrial distillation column.

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In ultra-low data rate wireless sensor networks (WSNs) waking up just to listen to a beacon every superframe can be a major waste of energy. This study introduces MedMAC, a medium access protocol for ultra-low data rate WSNs that achieves significant energy efficiency through a novel synchronisation mechanism. The new draft IEEE 802.15.6 standard for body area networks includes a sub-class of applications such as medical implantable devices and long-term micro miniature sensors with ultra-low power requirements. It will be desirable for these devices to have 10 years or more of operation between battery changes, or to have average current requirements matched to energy harvesting technology. Simulation results are presented to show that the MedMAC allows nodes to maintain synchronisation to the network while sleeping through many beacons with a significant increase in energy efficiency during periods of particularly low data transfer. Results from a comparative analysis of MedMAC and IEEE 802.15.6 MAC show that MedMAC has superior efficiency with energy savings of between 25 and 87 for the presented scenarios. © 2011 The Institution of Engineering and Technology.

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This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 GigaFlops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realize the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilization of a library of parameterizable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.

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Privacy region protection in video surveillance systems is an active topic at present. In previous research, a binary mask mechanism has been developed to indicate the privacy region; however this incurs a significant bitrate overhead. In this paper, an adaptive binary mask is proposed to represent the privacy region. In a practical privacy region protection application, in which the privacy region typically occupies less than half of the overall frame and is rectangular or approximately rectangular, the proposed adaptive binary mask can effectively reduce the bitrate overhead. The proposed method can also be easily applied to the FMO mechanism of H.264/AVC, providing both error resilience and a lower bitrate overhead.

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Fixed and wireless networks are increasingly converging towards common connectivity with IP-based core networks. Providing effective end-to-end resource and QoS management in such complex heterogeneous converged network scenarios requires unified, adaptive and scalable solutions to integrate and co-ordinate diverse QoS mechanisms of different access technologies with IP-based QoS. Policy-Based Network Management (PBNM) is one approach that could be employed to address this challenge. Hence, a policy-based framework for end-to-end QoS management in converged networks, CNQF (Converged Networks QoS Management Framework) has been proposed within our project. In this paper, the CNQF architecture, a Java implementation of its prototype and experimental validation of key elements are discussed. We then present a fuzzy-based CNQF resource management approach and study the performance of our implementation with real traffic flows on an experimental testbed. The results demonstrate the efficacy of our resource-adaptive approach for practical PBNM systems

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We compare the achievable performance of adaptive beamforming (A-BF) and adaptive orthogonal space time block coding (A-OSTBC) with outdated channel feedback. We extend our single user setup to multiuser diversity systems employing adaptive modulation, and illustrate the impact of feedback delay on the multiuser diversity gain with either A-OSTBC or A-BF. Using closed-form expressions for spectral efficiency and average BER of a multiuser diversity system derived in this paper, we prove that the A-BF scheme outperforms the A-OSTBC scheme with no feedback delay. However, when the feedback delay is large, the A-OSTBC scheme achieves better performance due to the reduced diversity advantage of A-BF. We observe that more transmit antennas bring higher spectral efficiency for BF. With small feedback delay, this becomes inverted using OSTBC, due to the effect of channel-hardening. Interestingly, however, we show that A-OSTBC with multiple users enjoys improved spectral efficiency when the number of transmit antennas is increased and the feedback delay is significant

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Abstract-Channel state information (CSI) at the transmitter can be used to adapt transmission rate or antenna gains in multi-antenna systems. We propose a rate-adaptive M-QAM scheme equipped with orthogonal space-time block coding with simple outdated, finite-rate feedback over independent flat fading channels. We obtain closed-form expressions for the average BER and throughput for our scheme, and analyze the effects of possibly delayed feedback on the performance gains. We derive optimal switching thresholds maximizing the average throughput under average and outage BER constraints with outdated feedback. Our numerical results illustrate the immunity of our optimal thresholds to delayed feedback.

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In this paper, we investigate adaptive linear combinations of graph coloring heuristics with a heuristic modifier to address the examination timetabling problem. We invoke a normalisation strategy for each parameter in order to generalise the specific problem data. Two graph coloring heuristics were used in this study (largest degree and saturation degree). A score for the difficulty of assigning each examination was obtained from an adaptive linear combination of these two heuristics and examinations in the list were ordered based on this value. The examinations with the score value representing the higher difficulty were chosen for scheduling based on two strategies. We tested for single and multiple heuristics with and without a heuristic modifier with different combinations of weight values for each parameter on the Toronto and ITC2007 benchmark data sets. We observed that the combination of multiple heuristics with a heuristic modifier offers an effective way to obtain good solution quality. Experimental results demonstrate that our approach delivers promising results. We conclude that this adaptive linear combination of heuristics is a highly effective method and simple to implement.

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In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration system level interactions and ensuring that under any change of operating conditions only the "lesscrucial" computations, that contribute less to block/system output quality, are affected. The design methodology applied to a DCT/IDCT system shows large power benefits (up to 69%) at reasonable image quality while tolerating errors induced by varying operating conditions (VOS, process variations, channel noise). Interestingly, the proposed IDCT scheme conceals channel noise at scaled voltages. ©2009 IEEE.

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In this paper, we explore various arithmetic units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling. Such hybrid units result from mixing right amount of fast arithmetic into the slower ones. Simulations on different hybrid adder and multipliers in BPTM 70 nm technology show 18%-50% improvements in power compared to standard adders with only 2%-8% increase in die-area at iso-yield. These optimized datapath units can be used to construct voltage scalable robust ALUs that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching. © 2009 IEEE.

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The design and VLSI implementation of two key components of the class-IV partial response maximum likelihood channel (PR-IV) the adaptive filter and the Viterbi decoder are described. These blocks are implemented using parameterised VHDL modules, from a library of common digital signal processing (DSP) and arithmetic functions. Design studies, based on 0.6 micron 3.3V standard cell processes, indicate that worst case sampling rates of 49 mega-samples per second are achievable for this system, with proportionally high sampling rates for full custom designs and smaller dimension processes. Significant increases in the sampling rate, from 49 MHz to approximately 180 MHz, can be achieved by operating four filter modules in parallel, and this implementation has 50% lower power consumption than a pipelined filter operating at the same speed.