Air quality and climate impacts of alternative bus technologies in Greater London.

The environmental impact of diesel-fueled buses can potentially be reduced by the adoption of alternative propulsion technologies such as lean-burn compressed natural gas (LB-CNG) or hybrid electric buses (HEB), and emissions control strategies such as a continuously regenerating trap (CRT), exhaust gas recirculation (EGR), or selective catalytic reduction with trap (SCRT). This study assessed the environmental costs and benefits of these bus technologies in Greater London relative to the existing fleet and characterized emissions changes due to alternative technologies. We found a >30% increase in CO2 equivalent (CO2e) emissions for CNG buses, a <5% change for exhaust treatment scenarios, and a 13% (90% confidence interval 3.8-20.9%) reduction for HEB relative to baseline CO2e emissions. A multiscale regional chemistry-transport model quantified the impact of alternative bus technologies on air quality, which was then related to premature mortality risk. We found the largest decrease in population exposure (about 83%) to particulate matter (PM2.5) occurred with LB-CNG buses. Monetized environmental and investment costs relative to the baseline gave estimated net present cost of LB-CNG or HEB conversion to be $187 million ($73 million to $301 million) or $36 million ($-25 million to $102 million), respectively, while EGR or SCRT estimated net present costs were $19 million ($7 million to $32 million) or $15 million ($8 million to $23 million), respectively.

A 40 Gb/s optical bus for optical backplane interconnections

Optical technologies have received large interest in recent years for use in board-level interconnects. Polymer multimode waveguides in particular, constitute a promising technology for high-capacity optical backplanes as they can be cost-effectively integrated onto conventional printed circuit boards (PCBs). This paper presents the first optical backplane demonstrator based on the use of PCB-integrated polymer multimode waveguides and a regenerative shared bus architecture. The backplane demonstrator is formed with commercially-available low-cost electronic and photonic components onto conventional FR4 substrates and comprises two opto-electronic (OE) bus modules interconnected via a prototype regenerator unit. The system enables interconnection between the connected cards over four optical channels, each operating at 10 Gb/s. Bus extension is achieved by cascading OE bus modules via 3R regenerator units, overcoming therefore the inherent limitation of optical bus topologies in the maximum number of cards that can be connected to the bus. Details of the design, fabrication, and assembly of the different parts of this optical bus backplane are presented and related optical and data transmission characterisation studies are reported. The optical layer of the OE bus modules comprises a four-channel three-card waveguide layout that is compatible with VCSEL/PD arrays and ribbon fibres. All on-board optical paths exhibit insertion losses below 13 dB and intra-channel crosstalk lower than -29 dB. The robustness of the signal distribution from the bus inputs to all respective bus output ports in the presence of input misalignment is demonstrated, while 1 dB input alignment tolerances of approximately ±10 μm are obtained. The electrical layer of the OE bus modules comprises the essential driving circuitry for 1×4 VCSEL and PD arrays and the corresponding control and power regulation circuits. The interface between the optical and electrical layers of the bus modules is achieved with simple OE connectors that enable end-fired optical coupling into and out of the on-board polymer waveguides. The backplane demonstrator achieves error-free (BER < 10-12) 10 Gb/s data transmission over each optical channel, enabling therefore, an aggregate interconnection capacity of 40 Gb/s between any connected cards. © 1983-2012 IEEE.

Wideband wireless over fiber systems

Broadband radio over fiber systems, which can simultaneously distribute multiple wireless services and enable remote sensing, are reviewed. The systems are used to demonstrate improved remote passive RFID tag detection through the use of multiple antennas. © 2009 Optical Society of America.

Radio over fibre technologies for wideband in-building wireless coverage

This paper describes the use of radio over multimode fibre networks to allow wideband wireless coverage in building environments. It will cover basic principles, commercial applications of such networks and their extension to provide a converged communications/sensing system. © 2009 Optical Society of America.

Analysis of coupled microcircular resonators coupled to a bus waveguide with high output efficiency

Coupled microcircular resonators tangentially coupled to a bus waveguide, which is between the resonators, are numerically investigated by the finite-difference time-domain technique. For symmetrically coupled microcircular resonators with refractive index of 3.2, radius of 2 mu m, and width of the bus waveguide of 0.4 mu m, a mode Q factor of the order of 105 is obtained for a mode at the frequency of 243 THz. An output coupling efficiency of as high as 0.99 is calculated for a mode with a Q factor ranging from 10(3) to 10(4). The mode Q factor is 2 orders larger than that of the modes confined in a single circular resonator tangentially coupled to the same bus waveguide. Furthermore, the high Q traveling modes in the coupled microcircular resonators are suitable for optical single processing.

Smart universal multiple-valued logic gates by transferring single electrons

This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SEs). The logic gates are based on MOSFET based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the MOSFET based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.

Compact universal logic gates realized using quantization of current in nanodevices

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

A Complex BPF with On Chip Auto-tuning Architecture for Wireless Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18um standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 16.2dBm, with 50 Omega as the source impedance. The input referred noise is about 80uV(rms). The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28 x 0.22 mm(2), less than 1/8 of that of the main-filter which is 0.92 x 0.59 mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

Low Power Integrated Circuits for Wireless Neural Recording Applications

A group of prototype integrated circuits are presented for a wireless neural recording micro-system. An inductive link was built for transcutaneous wireless power transfer and data transmission. Power and data were transmitted by a pair of coils on a same carrier frequency. The integrated receiver circuitry was composed of a full-wave bridge rectifier, a voltage regulator, a date recovery circuit, a clock recovery circuit and a power detector. The amplifiers were designed with a limited bandwidth for neural signals acquisition. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments. 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 MHz carrier within 10 mm. The total gain of 60 dB was obtained by the preamplifier and a main amplifier at 0.95Hz - 13.41 KHz with 0.215 mW power dissipation. The power consumption of the 100 MHz ASK transmitter is 0.374 mW. All the integrated circuits operated under a 3.3 V power supply except the voltage regulator.

Implantable Microsystem for Wireless Neural Recording Applications

A prototype microsystem is presented for wireless neural recording application. An inductive link was built for transcutaneous wireless power transfer and data transmission. Total 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 - 5 MHz with a distance of 0-10 mm. The integrated amplifiers were designed with a limited bandwidth for neural signals acquisition. The gain of 60 dB was obtained by preamplifier at 7 Hz - 3 KHz. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments with 0.374 - 2 mW power comsumption and a maximum data rate of 500 Kbps at 100 MHz. All the integrated circuits modules except the power recovery circuit were tested or stimulated under a 3.3 V power supply, and fabricated in standard CMOS processing.

VLSI architecture of a K-best detector for MIMO--OFDM wireless communication systems

The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.