Virtex FPGA Implementation of a Pipelined Adaptive LMS Predictor for Electronic Support Measures Receivers

High-speed field-programmable gate array (FPGA) implementations of an adaptive least mean square (LMS) filter with application in an electronic support measures (ESM) digital receiver, are presented. They employ "fine-grained" pipelining, i.e., pipelining within the processor and result in an increased output latency when used in the LMS recursive system. Therefore, the major challenge is to maintain a low latency output whilst increasing the pipeline stage in the filter for higher speeds. Using the delayed LMS (DLMS) algorithm, fine-grained pipelined FPGA implementations using both the direct form (DF) and the transposed form (TF) are considered and compared. It is shown that the direct form LMS filter utilizes the FPGA resources more efficiently thereby allowing a 120 MHz sampling rate.

Design of silicon IP cores for biorthogonal wavelet transforms

A methodology for rapid silicon design of biorthogonal wavelet transform systems has been developed. This is based on generic, scalable architectures for the forward and inverse wavelet filters. These architectures offer efficient hardware utilisation by combining the linear phase property of biorthogonal filters with decimation and interpolation. The resulting designs have been parameterised in terms of types of wavelet and wordlengths for data and coefficients. Control circuitry is embedded within these cores that allows them to be cascaded for any desired level of decomposition without any interface logic. The time to produce silicon designs for a biorthogonal wavelet system is only the time required to run synthesis and layout tools with no further design effort required. The resulting silicon cores produced are comparable in area and performance to hand-crafted designs. These designs are also portable across a range of foundries and are suitable for FPGA and PLD implementations.

Linear QR architecture for a single chip adaptive beamformer

This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.

The portrait of the first poster artists of Spanish cinema: From the genre scene to the realistic portrait

The article, which is part of a more detailed piece of work, aims to highlight the use of the portrait on the film posters of the first Spanish poster artists before the Star-System was introduced in Spain. For this it is posed the evolution that occurs in the representation of the characters in the film poster from the second decade to the beginning of the thirties in the twentieth century, a historical period of profound influences of the artistic and advertising vanguards in our poster artists´ work. However, in the late twenties moving from the simple inclusion of the scene based on the picture of a film, to the chromatic and realistic representation of the star´s face. These were the years when the influence of the major North American studios began to show in Spain. Nevertheless, it highlights their technical and compositional freedom and their influence on subsequent poster artists, as many of them will integrate the portraits and settings on their posters, following the guidelines of the major studios or the independent ones. But without forgetting their own personal way of painting the film stars’ faces on their posters.

The Design Process- Making It Relevant For Students

Within the ever-changing arenas of architectural design and education, the core element of architectural education remains: that of the design process. The consideration of how to design in addition to what to design presents architectural educators with that most constant and demanding challenge of how do we best teach the design process?

This challenge is arguably most acute at a student's early stages of their architectural education. In their first years in architecture, students will commonly concentrate on the end product rather than the process. This is, in many ways, understandable. A great deal of time, money and effort go into their final presentations. They believe that it is what is on the wall that is going to be assessed. Armed with new computer skills, they want to produce eye-catching graphics that are often no more than a celebration of a CAD package. In an era of increasing speed, immediacy of information and powerful advertising it is unsurprising that students want to race quickly to presenting an end-product.

Recognising that trend, new teaching methods and models were introduced into the second year undergraduate studio over the past two years at Queen's University Belfast, aimed at promoting student self-reflection and making the design process more relevant to the students. This paper will first generate a critical discussion on the difficulties associated with the design process before outlining some of the methods employed to help promote the following; an understanding of concept, personalisation of the design process for the individual student; adding realism and value to the design process and finally, getting he students to play to their strengths in illustrating their design process like an element of product. Frameworks, examples, outcomes and student feedback will all be presented to help illustrate the effectiveness of the new strategies employed in making the design process firstly, more relevant and therefore secondly, of greater value, to the architecture student.

Design and implementation of a field programmable CRC circuit architecture

The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s. © 2006 IEEE.

A scalable packet sorting circuit for high-speed WFQ packet scheduling

A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.

Lack of Association Between the Trp719Arg Polymorphism in Kinesin-Like Protein-6 and Coronary Artery Disease in 19 Case-Control Studies

Objectives: We sought to replicate the association between the kinesin-like protein 6 (KIF6) Trp719Arg polymorphism (rs20455), and clinical coronary artery disease (CAD).
Background: Recent prospective studies suggest that carriers of the 719Arg allele in KIF6 are at increased risk of clinical CAD compared with noncarriers.
Methods: The KIF6 Trp719Arg polymorphism (rs20455) was genotyped in 19 case-control studies of nonfatal CAD either as part of a genome-wide association study or in a formal attempt to replicate the initial positive reports.
Results: A total of 17,000 cases and 39,369 controls of European descent as well as a modest number of South Asians, African Americans, Hispanics, East Asians, and admixed cases and controls were successfully genotyped. None of the 19 studies demonstrated an increased risk of CAD in carriers of the 719Arg allele compared with noncarriers. Regression analyses and fixed-effects meta-analyses ruled out with high degree of confidence an increase of <2% in the risk of CAD among European 719Arg carriers. We also observed no increase in the risk of CAD among 719Arg carriers in the subset of Europeans with early-onset disease (younger than 50 years of age for men and younger than 60 years of age for women) compared with similarly aged controls as well as all non-European subgroups.
Conclusions: The KIF6 Trp719Arg polymorphism was not associated with the risk of clinical CAD in this large replication study.

A framework for collaborative working environments

To utilize the advantages of existing and emerging Internet techniques and to meet the demands for a new generation of collaborative working environments, a framework with an upperware–middleware architecture is proposed, which consists of four layers: resource layer, middleware layer, upperware layer and application layer. The upperware contains intelligent agents and plug/play facilities; the former coordinates and controls multiple middleware techniques such as Grid computing, Web-services and mobile agents, while the latter are used for the applications, such as semantic CAD, to plug and loose couple into the system. The method of migrating legacy software using automatic wrapper generation technique is also presented. A prototype mobile environment for collaborative product design is presented to illustrate the utilization of the CWE framework in collaborative design and manufacture.

Application of Internet techniques into online collaborative design and manufacture

A research project in Web-enabled collaborative design and manufacture has been conducted. The major tasks of the project include the development of a Web-enabled environment for collaboration, online collaborative CAD/CAM, remote execution of large size programs (RELSP), and distributed product design. The tasks and Web/Internet techniques involved are presented first, followed by detail description of two approaches developed for implementation of the research: (1) a client-server approach for RELSP, where the following Internet techniques are utilized: CORBA, Microsoft’s Internet information server, Tomcat server, JDBC and ODBC; (2) Web-Services supported collaborative CAD which enables geographically dispersed designers jointly conduct a design task in the way of speaking and seeing each other and instantaneously modifying the CAD drawing online.

Large-scale association analysis identifies 13 new susceptibility loci for coronary artery disease

We performed a meta-analysis of 14 genome-wide association studies of coronary artery disease (CAD) comprising 22,233 individuals with CAD (cases) and 64,762 controls of European descent followed by genotyping of top association signals in 56,682 additional individuals. This analysis identified 13 loci newly associated with CAD at P < 5 x 10(-8) and confirmed the association of 10 of 12 previously reported CAD loci. The 13 new loci showed risk allele frequencies ranging from 0.13 to 0.91 and were associated with a 6% to 17% increase in the risk of CAD per allele. Notably, only three of the new loci showed significant association with traditional CAD risk factors and the majority lie in gene regions not previously implicated in the pathogenesis of CAD. Finally, five of the new CAD risk loci appear to have pleiotropic effects, showing strong association with various other human diseases or traits.

An On Demand Queue Management Architecture for a Programmable Traffic Manager

A queue manager (QM) is a core traffic management (TM) function used to provide per-flow queuing in access andmetro networks; however current designs have limited scalability. An on-demand QM (OD-QM) which is part of a new modular field-programmable gate-array (FPGA)-based TM is presented that dynamically maps active flows to the available physical resources; its scalability is derived from exploiting the observation that there are only a few hundred active flows in a high speed network. Simulations with real traffic show that it is a scalable, cost-effective approach that enhances per-flow queuing performance, thereby allowing per-flow QM without the need for extra external memory at speeds up to 10 Gbps. It utilizes 2.3%–16.3% of a Xilinx XC5VSX50t FPGA and works at 111 MHz.