Characterization of template switching and recombination during Moloney murine leukemia virus replication

Retroviruses uniquely co-package two copies of their genomic RNA within each virion. The two copies are used as templates for synthesis of the proviral DNA during the process of reverse transcription. Two template switches are required to complete retroviral DNA synthesis by the retroviral enzyme, reverse transcriptase. With two RNA genomes present in the virion, reverse transcriptase can make template switches utilizing only one of the RNA templates (intramolecular) or utilizing both RNA templates (intermolecular) during the process of reverse transcription. The results presented in this study show that during a single cycle of Moloney murine leukemia virus replication, both nonrecombinant and recombinant proviruses predominantly underwent intramolecular minus- and plus-strand transfers during the process of reverse transcription. This is the first study to examine the nature of the required template switches occurring during MLV replication and these results support the previous findings for SNV, and the hypothesis that the required template switches are ordered events. This study also determined rates for deletion and a rate of recombination for a single cycle of MLV replication. The rates reported here are comparable to the rates previously reported for both SNV and MLV. ^

High quality InAlN single layers lattice-matched to GaN grown by molecular beam epitaxy

We report on properties of high quality ~60 nm thick InAlN layers nearly in-plane lattice-matched to GaN, grown on c-plane GaN-on-sapphire templates by plasma-assisted molecular beam epitaxy. Excellent crystalline quality and low surface roughness are confirmed by X-ray diffraction, transmission electron microscopy, and atomic force microscopy. High annular dark field observations reveal a periodic in-plane indium content variation (8 nm period), whereas optical measurements evidence certain residual absorption below the band-gap. The indium fluctuation is estimated to be +/- 1.2% around the nominal 17% indium content via plasmon energy oscillations assessed by electron energy loss spectroscopy with sub-nanometric spatial resolution.

Selective area growth of a- and c-plane GaN nanocolumns by molecular beam epitaxy using colloidal nanolithography

Selective area growth of a-plane GaN nanocolumns by molecular beam epitaxy was performed for the first time on a-plane GaN templates. Ti masks with 150 nm diameter nanoholes were fabricated by colloidal lithography, an easy, fast and cheap process capable to handle large areas. Even though colloidal lithography does not provide a perfect geometrical arrangement like e-beam lithography, it produces a very homogeneous mask in terms of nanohole diameter and density, and is used here for the first time for the selective area growth of GaN. Selective area growth of a-plane GaN nanocolumns is compared, in terms of anisotropic lateral and vertical growth rates, with GaN nanocolumns grown selectively on the c-plane

One dimensional exciton luminescence induced by extended defects in nonpolar (Al,Ga)N/GaN quantum wells

In this study, we present the optical properties of nonpolar GaN/(Al,Ga)N single quantum wells (QWs) grown on either a- or m-plane GaN templates for Al contents set below 15%. In order to reduce the density of extended defects, the templates have been processed using the epitaxial lateral overgrowth technique. As expected for polarization-free heterostructures, the larger the QW width for a given Al content, the narrower the QW emission line. In structures with an Al content set to 5 or 10%, we also observe emission from excitons bound to the intersection of I1-type basal plane stacking faults (BSFs) with the QW. Similarly to what is seen in bulk material, the temperature dependence of BSF-bound QW exciton luminescence reveals intra-BSF localization. A qualitative model evidences the large spatial extension of the wavefunction of these BSF-bound QW excitons, making them extremely sensitive to potential fluctuations located in and away from BSF. Finally, polarization-dependent measurements show a strong emission anisotropy for BSF-bound QW excitons, which is related to their one-dimensional character and that confirms that the intersection between a BSF and a GaN/(Al,Ga)N QW can be described as a quantum wire.

Design and evaluation of acceleration strategies for speeding up the development of dialog applications

In this paper, we describe a complete development platform that features different innovative acceleration strategies, not included in any other current platform, that simplify and speed up the definition of the different elements required to design a spoken dialog service. The proposed accelerations are mainly based on using the information from the backend database schema and contents, as well as cumulative information produced throughout the different steps in the design. Thanks to these accelerations, the interaction between the designer and the platform is improved, and in most cases the design is reduced to simple confirmations of the “proposals” that the platform dynamically provides at each step. In addition, the platform provides several other accelerations such as configurable templates that can be used to define the different tasks in the service or the dialogs to obtain or show information to the user, automatic proposals for the best way to request slot contents from the user (i.e. using mixed-initiative forms or directed forms), an assistant that offers the set of more probable actions required to complete the definition of the different tasks in the application, or another assistant for solving specific modality details such as confirmations of user answers or how to present them the lists of retrieved results after querying the backend database. Additionally, the platform also allows the creation of speech grammars and prompts, database access functions, and the possibility of using mixed initiative and over-answering dialogs. In the paper we also describe in detail each assistant in the platform, emphasizing the different kind of methodologies followed to facilitate the design process at each one. Finally, we describe the results obtained in both a subjective and an objective evaluation with different designers that confirm the viability, usefulness, and functionality of the proposed accelerations. Thanks to the accelerations, the design time is reduced in more than 56% and the number of keystrokes by 84%.

Dimensión política y de gestión de la Huella Hídrica

El ciclo hidrológico proporciona anualmente 110,000 Km3 en forma de precipitaciones de lluvia y nieve (L'Vovich et al., 1990). Globalmente, el 37% de esas precipitaciones se destina a alimentar ríos, acuíferos, lagos y otros sistemas acuáticos, mientras que el 63% restante, se almacena en la reserva de agua del suelo y contribuye a mantener la productividad primaria de los sistemas agrícolas y forestales. Según las distintas estimaciones, el volumen de agua que actualmente se extrae de los sistemas acuáticos para uso humano a escala global varía entre 3100 y 4400 Km3 (Postel et al., 1996; Rosegrant et al., 2002; Falkenmark y Rockström, 2004; Oki y Kanae 2006; Gleick et al., 2008). Teniendo en cuenta que la cantidad de agua que puede ser captada de forma sostenible de estos sistemas es de aproximadamente 10.200 Km3 (Postel et al., 1996), la apropiación actual de este recurso representa en torno al 31 y 44%.

Stress Detection by means of Stress Physiological Template

This paper describes a stress detection system based on fuzzy logic and two physiological signals: Galvanic Skin Response and Heart Rate. Instead of providing a global stress classification, this approach creates an individual stress templates, gathering the behaviour of individuals under situations with different degrees of stress. The proposed method is able to detect stress properly with a rate of 99.5%, being evaluated with a database of 80 individuals. This result improves former approaches in the literature and well-known machine learning techniques like SVM, k-NN, GMM and Linear Discriminant Analysis. Finally, the proposed method is highly suitable for real-time applications

An image segmentation based on a genetic algorithm for determining soil coverage by crop residues

Determination of the soil coverage by crop residues after ploughing is a fundamental element of Conservation Agriculture. This paper presents the application of genetic algorithms employed during the fine tuning of the segmentation process of a digital image with the aim of automatically quantifying the residue coverage. In other words, the objective is to achieve a segmentation that would permit the discrimination of the texture of the residue so that the output of the segmentation process is a binary image in which residue zones are isolated from the rest. The RGB images used come from a sample of images in which sections of terrain were photographed with a conventional camera positioned in zenith orientation atop a tripod. The images were taken outdoors under uncontrolled lighting conditions. Up to 92% similarity was achieved between the images obtained by the segmentation process proposed in this paper and the templates made by an elaborate manual tracing process. In addition to the proposed segmentation procedure and the fine tuning procedure that was developed, a global quantification of the soil coverage by residues for the sampled area was achieved that differed by only 0.85% from the quantification obtained using template images. Moreover, the proposed method does not depend on the type of residue present in the image. The study was conducted at the experimental farm “El Encín” in Alcalá de Henares (Madrid, Spain).

Distributed www programming using (Ciao-) prolog and the pillow library

We discuss from a practical point of view a number of ssues involved in writing distributed Internet and WWW applications using LP/CLP systems. We describe PiLLoW, a publicdomain Internet and WWW programming library for LP/CLP systems that we have designed in order to simplify the process of writing such applications. PiLLoW provides facilities for accessing documents and code on the WWW; parsing, manipulating and generating HTML and XML structured documents and data; producing HTML forms; writing form handlers and CGI-scripts; and processing HTML/XML templates. An important contribution of PÍ'LLOW is to model HTML/XML code (and, thus, the content of WWW pages) as terms. The PÍ'LLOW library has been developed in the context of the Ciao Prolog system, but it has been adapted to a number of popular LP/CLP systems, supporting most of its functionality. We also describe the use of concurrency and a highlevel model of client-server interaction, Ciao Prolog's active modules, in the context of WWW programming. We propose a solution for client-side downloading and execution of Prolog code, using generic browsers. Finally, we also provide an overview of related work on the topic.

Crecimiento, fabricación y caracterización de heteroestructuras y nanocolumnas ordenadas basadas en nitruros del grupo III para aplicaciones sensoras

Esta memoria está basada en el crecimiento y caracterización de heteroestructuras Al(Ga)N/GaN y nanocolumnas ordenadas de GaN, y su aplicación en sensores químicos. El método de crecimiento ha sido la epitaxia de haces moleculares asistida por plasma (PAMBE). En el caso de las heteroestructuras Al(Ga)N/GaN, se han crecido barreras de distinto espesor y composición, desde AlN de 5 nm, hasta AlGaN de 35 nm. Además de una caracterización morfológica, estructural y eléctrica básica de las capas, también se han fabricado a partir de ellas dispositivos tipo HEMTs. La caracterización eléctrica de dichos dispositivos (carga y movilidad de en el canal bidimensional) indica que las mejores heteroestructuras son aquellas con un espesor de barrera intermedio (alrededor de 20 nm). Sin embargo, un objetivo importante de esta Tesis ha sido verificar las ventajas que podían tener los sensores basados en heteroestructuras AlN/GaN (frente a los típicos basados en AlGaN/GaN), con espesores de barrera muy finos (alrededor de 5 nm), ya que el canal de conducción que se modula por efecto de cambios químicos está más cerca de la superficie en donde ocurren dichos cambios químicos. De esta manera, se han utilizado los dispositivos tipo HEMTs como sensores químicos de pH (ISFETs), y se ha comprobado la mayor sensibilidad (variación de corriente frente a cambios de pH, Ids/pH) en los sensores basados en AlN/GaN frente a los basados en AlGaN/GaN. La mayor sensibilidad es incluso más patente en aplicaciones en las que no se utiliza un electrodo de referencia. Se han fabricado y caracterizado dispositivos ISFET similares utilizando capas compactas de InN. Estos sensores presentan peor estabilidad que los basados en Al(Ga)N/GaN, aunque la sensibilidad superficial al pH era la misma (Vgs/pH), y su sensibilidad en terminos de corriente de canal (Ids/pH) arroja valores intermedios entre los ISFET basados en AlN/GaN y los valores de los basados en AlGaN/GaN. Para continuar con la comparación entre dispositivos basados en Al(Ga)N/GaN, se fabricaron ISFETs con el área sensible más pequeña (35 x 35 m2), de tamaño similar a los dispositivos destinados a las medidas de actividad celular. Sometiendo los dispositivos a pulsos de voltaje en su área sensible, la respuesta de los dispositivos de AlN presentaron menor ruido que los basados en AlGaN. El ruido en la corriente para dispositivos de AlN, donde el encapsulado no ha sido optimizado, fue tan bajo como 8.9 nA (valor rms), y el ruido equivalente en el potencial superficial 38.7 V. Estos valores son más bajos que los encontrados en los dispositivos típicos para la detección de actividad celular (basados en Si), y del orden de los mejores resultados encontrados en la literatura sobre AlGaN/GaN. Desde el punto de vista de la caracterización electro-química de las superficies de GaN e InN, se ha determinado su punto isoeléctrico. Dicho valor no había sido reportado en la literatura hasta el momento. El valor, determinado por medidas de “streaming potential”, es de 4.4 y 4 respectivamente. Este valor es una importante característica a tener en cuenta en sensores, en inmovilización electrostática o en la litografía coloidal. Esta última técnica se discute en esta memoria, y se aplica en el último bloque de investigación de esta Tesis (i.e. crecimiento ordenado). El último apartado de resultados experimentales de esta Tesis analiza el crecimiento selectivo de nanocolumnas ordenadas de GaN por MBE, utilizando mascaras de Ti con nanoagujeros. Se ha estudiado como los distintos parámetros de crecimiento (i.e. flujos de los elementos Ga y N, temperatura de crecimiento y diseño de la máscara) afectan a la selectividad y a la morfología de las nanocolumnas. Se ha conseguido con éxito el crecimiento selectivo sobre pseudosustratos de GaN con distinta orientación cristalina o polaridad; templates de GaN(0001)/zafiro, GaN(0001)/AlN/Si, GaN(000-1)/Si y GaN(11-20)/zafiro. Se ha verificado experimentalmente la alta calidad cristalina de las nanocolumnas ordenadas, y su mayor estabilidad térmica comparada con las capas compactas del mismo material. Las nanocolumnas ordenadas de nitruros del grupo III tienen una clara aplicación en el campo de la optoelectrónica, principalmente para nanoemisores de luz blanca. Sin embargo, en esta Tesis se proponen como alternativa a la utilización de capas compactas o nanocolumnas auto-ensambladas en sensores. Las nanocolumnas auto-ensambladas de GaN, debido a su alta razón superficie/volumen, son muy prometedoras en el campo de los sensores, pero su amplia dispersión en dimensiones (altura y diámetro) supone un problema para el procesado y funcionamiento de dispositivos reales. En ese aspecto, las nanocolumnas ordenadas son más robustas y homogéneas, manteniendo una alta relación superficie/volumen. Como primer experimento en el ámbito de los sensores, se ha estudiado como se ve afectada la emisión de fotoluminiscencia de las NCs ordenadas al estar expuestas al aire o al vacio. Se observa una fuerte caída en la intensidad de la fotoluminiscencia cuando las nanocolumnas están expuestas al aire (probablemente por la foto-adsorción de oxigeno en la superficie), como ya había sido documentado anteriormente en nanocolumnas auto-ensambladas. Este experimento abre el camino para futuros sensores basados en nanocolumnas ordenadas. Abstract This manuscript deals with the growth and characterization of Al(Ga)N/GaN heterostructures and GaN ordered nanocolumns, and their application in chemical sensors. The growth technique has been the plasma-assisted molecular beam epitaxy (PAMBE). In the case of Al(Ga)N/GaN heterostructures, barriers of different thickness and composition, from AlN (5 nm) to AlGaN (35 nm) have been grown. Besides the basic morphological, structural and electrical characterization of the layers, HEMT devices have been fabricated based on these layers. The best electrical characteristics (larger carriers concentration and mobility in the two dimensional electron gas) are those in AlGaN/GaN heterostructures with a medium thickness (around 20 nm). However, one of the goals of this Thesis has been to verify the advantages that sensors based on AlN/GaN (thickness around 7 nm) have compared to standard AlGaN/GaN, because the conduction channel to be modulated by chemical changes is closer to the sensitive area. In this way, HEMT devices have been used as chemical pH sensors (ISFETs), and the higher sensitivity (conductance change related to pH changes, Ids/pH) of AlN/GaN based sensors has been proved. The higher sensibility is even more obvious in application without reference electrode. Similar ISFETs devices have been fabricated based on InN compact layers. These devices show a poor stability, but its surface sensitivity to pH (Vgs/pH) and its sensibility (Ids/pH) yield values between the corresponding ones of AlN/GaN and AlGaN/GaN heterostructures. In order to a further comparison between Al(Ga)N/GaN based devices, ISFETs with smaller sensitive area (35 x 35 m2), similar to the ones used in cellular activity record, were fabricated and characterized. When the devices are subjected to a voltage pulse through the sensitive area, the response of AlN based devices shows lower noise than the ones based on AlGaN. The noise in the current of such a AlN based device, where the encapsulation has not been optimized, is as low as 8.9 nA (rms value), and the equivalent noise to the surface potential is 38.7 V. These values are lower than the found in typical devices used for cellular activity recording (based on Si), and in the range of the best published results on AlGaN/GaN. From the point of view of the electrochemical characterization of GaN and InN surfaces, their isoelectric point has been experimentally determined. Such a value is the first time reported for GaN and InN surfaces. These values are determined by “streaming potential”, being pH 4.4 and 4, respectively. Isoelectric point value is an important characteristic in sensors, electrostatic immobilization or in colloidal lithography. In particular, colloidal lithography has been optimized in this Thesis for GaN surfaces, and applied in the last part of experimental results (i.e. ordered growth). The last block of this Thesis is focused on the selective area growth of GaN nanocolumns by MBE, using Ti masks decorated with nanoholes. The effect of the different growth parameters (Ga and N fluxes, growth temperature and mask design) is studied, in particular their impact in the selectivity and in the morphology of the nanocolumns. Selective area growth has been successful performed on GaN templates with different orientation or polarity; GaN(0001)/sapphire, GaN(0001)/AlN/Si, GaN(000- 1)/Si and GaN(11-20)/sapphire. Ordered nanocolumns exhibit a high crystal quality, and a higher thermal stability (lower thermal decomposition) than the compact layers of the same material. Ordered nanocolumns based on III nitrides have a clear application in optoelectronics, mainly for white light nanoemitters. However, this Thesis proposes them as an alternative to compact layers and self-assembled nanocolumns in sensor applications. Self-assembled GaN nanocolumns are very appealing for sensor applications, due to their large surface/volume ratio. However, their large dispersion in heights and diameters are a problem in terms of processing and operation of real devices. In this aspect, ordered nanocolumns are more robust and homogeneous, keeping the large surface/volume ratio. As first experimental evidence of their sensor capabilities, ordered nanocolumns have been studied regarding their photoluminiscence on air and vacuum ambient. A big drop in the intensity is observed when the nanocolumns are exposed to air (probably because of the oxygen photo-adsortion), as was already reported in the case of self-assembled nanocolumns. This opens the way to future sensors based on ordered III nitrides nanocolumns.

Application of backend database contents and structure to the design of spoken dialog services

Current development platforms for designing spoken dialog services feature different kinds of strategies to help designers build, test, and deploy their applications. In general, these platforms are made up of several assistants that handle the different design stages (e.g. definition of the dialog flow, prompt and grammar definition, database connection, or to debug and test the running of the application). In spite of all the advances in this area, in general the process of designing spoken-based dialog services is a time consuming task that needs to be accelerated. In this paper we describe a complete development platform that reduces the design time by using different types of acceleration strategies based on using information from the data model structure and database contents, as well as cumulative information obtained throughout the successive steps in the design. Thanks to these accelerations, the interaction with the platform is simplified and the design is reduced, in most cases, to simple confirmations to the “proposals” that the platform automatically provides at each stage. Different kinds of proposals are available to complete the application flow such as the possibility of selecting which information slots should be requested to the user together, predefined templates for common dialogs, the most probable actions that make up each state defined in the flow, different solutions to solve specific speech-modality problems such as the presentation of the lists of retrieved results after querying the backend database. The platform also includes accelerations for creating speech grammars and prompts, and the SQL queries for accessing the database at runtime. Finally, we will describe the setup and results obtained in a simultaneous summative, subjective and objective evaluations with different designers used to test the usability of the proposed accelerations as well as their contribution to reducing the design time and interaction.

Ordered gan/ingan nanorods arrays grown by molecular beam epitaxy for phosphor-free white light emission

The basics of the self-assembled growth of GaN nanorods on Si(111) are reviewed. Morphology differences and optical properties are compared to those of GaN layers grown directly on Si(111). The effects of the growth temperature on the In incorporation in self-assembled InGaN nanorods grown on Si(111) is described. In addition, the inclusion of InGaN quantum disk structures into selfassembled GaN nanorods show clear confinement effects as a function of the quantum disk thickness. In order to overcome the properties dispersion and the intrinsic inhomogeneous nature of the self-assembled growth, the selective area growth of GaN nanorods on both, c-plane and a-plane GaN on sapphire templates, is addressed, with special emphasis on optical quality and morphology differences. The analysis of the optical emission from a single InGaN quantum disk is shown for both polar and non-polar nanorod orientations

Selective area growth and characterization of InGaN nano-disks implemented in GaN nanocolumns with different top morphologies

This work reports on the morphology control of the selective area growth of GaN-based nanostructures on c-plane GaN templates. By decreasing the substrate temperature, the nanostructures morphology changes from pyramidal islands (no vertical m-planes), to GaN nanocolumns with top semipolar r-planes, and further to GaN nanocolumns with top polar c-planes. When growing InGaN nano-disks embedded into the GaN nanocolumns, the different morphologies mentioned lead to different optical properties, due to the semi-polar and polar nature of the r-planes and c-planes involved. These differences are assessed by photoluminescence measurements at low temperature and correlated to the specific nano-disk geometry.

A Process Asset Library to support Software Process Improvement in Small Settings

A main factor to the success of any organization process improvement effort is the Process Asset Library implementation that provides a central database accessible by anyone at the organization. This repository includes any process support materials to help process deployment. Those materials are composed of organization's standard software process, software process related documentation, descriptions of the software life cycles, guidelines, examples, templates, and any artefacts that the organization considers useful to help the process improvement. This paper describe the structure and contents of the Web-based Process Asset Library for Small businesses and small groups within large organizations. This library is structured using CMMI as reference model in order to implement those Process Areas described by this model.

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.