System-on-a-Chip (SoC) based hardware acceleration in Register Transfer Level (RTL) design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

La cerámica del yacimiento arqueológico de Castillejo del Bonete (Terrinches, Ciudad Real). Estudio morfológico y tecnólogico

El presente trabajo incluye el estudio de un amplio conjunto cerámico perteneciente al yacimiento arqueológico de la Edad del Cobre y Edad del Bronce de Castillejo del Bonete. La muestra fue recuperada de distintas áreas del asentamiento durante la campaña de excavación de 2012. La investigación ha tenido como fin conocer mejor la relación forma-función de las vasijas, su proceso de fabricación, así como el modelo productivo y las posibles manifestaciones simbólicas presentes en el repertorio analizado. La metodología utilizada para cumplir con los objetivos se ha basado en la recopilación de datos, considerando una serie de variables morfológicas y tecnológicas, y su procesamiento con el empleo de técnicas estadísticas sencillas.

Late Bronze Age in Eastern Iberian Peninsula: Archaeological Bases and Periodization

Research surrounding the transition from II to I millennium cal BC in Eastern Iberian Peninsula has a large and extensive tradition of investigation. However, the chances to do research on this historical process have been limited by the lack of a well contextualized and dated stratigraphic sequence. For this reason, recent studies in this topic have followed the periodic proposals which were developed in closer regions and areas, especially in the South East and North East of the Peninsula. The investigation perspective about the Late Bronze in Eastern Iberian has however now improved, with the development of several archaeological investigations, the increase in the number of sites being dated and more recent studies into the region helping to bring about this change. As such, it is now in the correct state to be able to propose a new periodization and delve into the changes which occurred in the transition between 1500 and 725 cal BC.

Enhanced durability of Li-O2 batteries employing vertically standing Ti nanowire array supported cathodes

Ti nanowire arrays vertically standing on Ti foam prepared by a facile corrosion method were used as self-supported Li-O₂ battery cathodes. The batteries exhibited enhanced durability at high rate current densities (e.g. cycling 640 times at 5 A g^-1).

Olika chans beroende på födelsemånad : En kvantitativ undersökning av relative age effect på svenska längdskidgymnasier

Syfte Syftet med studien var att undersöka om relative age effect förekommer på svenska längdskidgymnasier bland antagna elever och hur eventuell förekomst ser ut bland flickor och pojkar samt hur det ser ut vid Riksidrottsgymnasierna och de Nationell Idrottsutbildningarna. Metod För att besvara syftet har statistisk data analyserats med hjälp av ett Pearson Chi2-test. Analysen har skett genom att undersöka födelsemånad, kön och inriktning bland antagna elever vid svenska längdskidgymnasier mellan åren 2010-2015. Resultat Resultatet visar att det finns signifikanta bevis på att relative age effect förkommer på svenska längdskidgymnasier (p= <0,05). Vid uppdelning av respektive utbildningsinriktning kunde det endast konstateras förekomst av relative age effect vid Riksidrottsgymnasierna, vid uppdelning av kön går det inte att säkerställa en signifikant förekomst av relative age effect. Slutsatser Studiens resultat visar att det förekommer relative age effect på svenska längdskidgymnasier, dock varierar den mellan de analyserade undervariablerna. Tydligast förekommer relative age effect vid Riksidrottsgymnasierna, medan det vid Nationell Idottsutbildning, kunde det inte konstateras bevis för en signifikant överrepresentation av elever födda under första kvartalet. När flickor och pojkar analyserades separat kunde ingen relative age effect konstateras. Det behövs mer forskning inom området för att få en överblick av konsekvenserna av relative age effect på längdskidgymnasier men även konsekvenserna för svensk längdskidåkning i stort.

Control de asistencia basado en reconocimiento robusto de fiducials: aplicación para sistemas de sobremesa

El objetivo de este trabajo ha sido el diseño y la implementación de una aplicación de escritorio para el control de la asistencia mediante el reconocimiento robusto de fiducials. La idea principal es que este sistema sea fiable y robusto y que nos permita ahorrar tiempo en el proceso de control de la asistencia. Para ello se ha diseñado un sistema que consta de dos partes, por un lado la aplicación de escritorio que haciendo uso de una webcam reconoce los fiducials y marca la asistencia del alumno en un hoja de cálculo de Google Drive y por otro lado una aplicación para dispositivos Android que genera un marcador a partir del NIU de cada alumno.

System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

Angiopoietin-1 promotes atherosclerosis by increasing the proportion of circulating Gr1 monocytes

Atherosclerosis is a chronic inflammatory disease occurring within the artery wall. A crucial step in atherogenesis is the infiltration and retention of monocytes into the subendothelial space of large arteries induced by chemokines and growth factors. Angiopoietin-1 (Ang-1) regulates angiogenesis and reduces vascular permeability and has also 15 been reported to promote monocyte migration in vitro. We investigated the role of Ang-1 in atherosclerosis-prone apolipoprotein-E (Apo-E) knockout mouse. Apo-E knockout (Apo-E-/-) mice fed a western or normal chow diet received a single iv injection of adenovirus encoding Ang-1 or control vector. Adenovirus-mediated systemic expression of Ang-1 induced a significant increase in early atherosclerotic lesion size and monocyte/macrophage accumulation compared with control animals receiving empty vector. Ang-1 significantly increased plasma MCP-1 and VEGF levels as measured by ELISA. FACS analysis showed that Ang-1 selectively increased inflammatory Gr1þmonocytes in the circulation, while the cell-surface 25 expression of CD11b, which mediates monocyte emigration, was significantly reduced. Ang-1 specifically increases circulating Gr1þinflammatory monocytes and increases monocyte/macrophage retention in atherosclerotic plaques, thereby contributing to development of atherosclerosis.

Hallazgos tomográficos como predictores del resultado funcional en edema macular secundario a oclusiones venosas retinianas

INTRODUCCIÓN: El Edema Macular (EM) es la principal causa de perdida de agudeza visual en pacientes con Oclusión Venosa Retiniana (OVR); luego del tratamiento, algunos pacientes persisten con mala agudeza visual. OBJETIVO: Realizar una Revisión Sistemática de la Literatura (RSL), para identificar la evidencia existente sobre factores tomográficos que predicen el resultado visual en pacientes con EM secundario a OVR. FUENTE DE LA INFORMACIÓN: PUBMED, MEDLINE, EMBASE, LILACS, COCHRANE, literatura gris. SELECCIÓN DE LOS ESTUDIOS: Ensayos Clínicos Controlados (ECC) y estudios observacionales analíticos. EXTRACCIÓN Y SÍNTESIS DE LOS DATOS: Dos investigadores seleccionaron los artículos de forma independiente. Se realizó una síntesis cualitativa de la información siguiendo las recomendaciones de la declaración PRISMA 2009. MEDIDAS Y DESENLACE PRINCIPAL: Grosor Retiniano Central (GRC), integridad de Banda Elipsoide e Integridad de Membrana Limitante Externa (MLE), determinados por SD OCT. El desenlace principal es la Agudeza Visual Mejor Corregida (AVMC) a los 6, 12,18 y/o 24 meses. RESULTADOS: Se identificaron 872 abstract y se incluyeron 8 artículos en el análisis cualitativo. Seis estudios evaluaron el GRC sin encontrar asociación con resultado visual final. Solo 2 estudios evaluaron y encontraron asociación estadísticamente significativa de la integridad de la MLE con el desenlace visual, Kang, H 2012 (r2 0,51 p 0,000), Rodriguez, F 2014 (p< 0,001). La integridad de la BE fue asociada a pronostico visual en 4 de 5 estudios que evaluaron esta variable, con resultados estadísticamente significativos. La AVMC de base también se asocio con desenlace visual en 4 de 5 estudios que la evaluaron. El mejor modelo que predice el resultado funcional según el estudio de Kang, H 2012 fue: Integridad de MLE, integridad de BE y AVMC de base (R2 0,671 p 0,000), a los 12 meses de seguimiento. CONCLUSION: La evidencia actual sugiere que la integridad de la BE y la MLE son predictores del resultados funcional en pacientes con EM secundario a OVR después de 6 o mas meses de seguimiento. Es necesario la realización de estudios controlados para llegar a resultados mas concluyentes.

Electronic structure and magnetism of Mn-doped GaSb for spintronic applications: A DFT study

We have carried out first-principles spin polarized calculations to obtain comprehensive information regarding the structural, magnetic, and electronic properties of the Mn-doped GaSb compound with dopant concentrations: x¼0.062, 0.083, 0.125, 0.25, and 0.50. The plane-wave pseudopotential method was used in order to calculate total energies and electronic structures. It was found that the MnGa substitution is the most stable configuration with a formation energy of 1.60 eV/Mn-atom. The calculated density of states shows that the half-metallic ferromagnetism is energetically stable for all dopant concentrations with a total magnetization of about 4.0 lB/Mn-atom. The results indicate that the magnetic ground state originates from the strong hybridization between Mn-d and Sb-p states, which agree with previous studies on Mn-doped wide gap semiconductors. This study gives new clues to the fabrication of diluted magnetic semiconductors