Nanoscale compositional analysis of NiTi shape memory alloy films deposited by DC magnetron sputtering

The formation of surface oxide layer as well as compositional changes along the thickness for NiTi shape memory alloy thin films deposited by direct current magnetron sputtering at substrate temperature of 300 degrees C in the as-deposited condition as well as in the postannealed (at 600 degrees C) condition have been thoroughly studied by using secondary ion mass spectroscopy, x-ray photoelectron spectroscopy, and scanning transmission electron microscopy-energy dispersive x-ray spectroscopy techniques. Formation of titanium oxide (predominantly titanium dioxide) layer was observed in both as-deposited and postannealed NiTi films, although the oxide layer was much thinner (8 nm) in as-deposited condition. The depletion of Ti and enrichment of Ni below the oxide layer in postannealed films also resulted in the formation of a graded microstructure consisting of titanium oxide, Ni3Ti, and B2 NiTi. A uniform composition of B2 NiTi was obtained in the postannealed film only below a depth of 200-250 nm from the surface. Postannealed film also exhibited formation of a ternary silicide (NixTiySi) at the film-substrate interface, whereas no silicide was seen in the as-deposited film. The formation of silicide also caused a depletion of Ni in the film in a region similar to 250-300 nm just above the film substrate interface. (C) 2013 American Vacuum Society.

Harmonic Analysis of DC-Link Capacitor Current in Sinusoidally Modulated Neutral-Point-Clamped Inverter

The voltage ripple and power loss in the DC-capacitor of a voltage source inverter depend on the harmonic currents flowing through the capacitor. This paper presents double Fourier series based harmonic analysis of DC capacitor current in a three-level neutral point clamped inverter, modulated with sine-triangle PWM. The analytical results are validated experimentally on a 5-kVA three-level inverter prototype. The results of the analysis are used for predicting the power loss in the DC capacitor.

A Three-Level Common-Mode Voltage Eliminated Inverter With Single DC Supply Using Flying Capacitor Inverter and Cascaded H-Bridge

A three-level common-mode voltage eliminated inverter with single dc supply using flying capacitor inverter and cascaded H-bridge has been proposed in this paper. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-bridge fails, the system can still be operated as a normal three-level inverter at full power. This inverter has many other advantages like use of single dc supply, making it possible for a back-to-back grid-tied converter application, improved reliability, etc.

A Reduced Device-Count Hybrid Multilevel Inverter Topology with single DC Source and Improved Fault Tolerance

A new hybrid multilevel power converter topology is presented in this paper. The proposed power converter topology uses only one DC source and floating capacitors charged to asymmetrical voltage levels, are used for generating different voltage levels. The SVPWM based control strategy used in this converter maintains the capacitor voltages at the required levels in the entire modulation range including the over-modulation region. For the voltage levels: nine and above, the number of components required in the proposed topology is significantly lower, compared to the conventional multilevel inverter topologies. The number of capacitors required in this topology reduces drastically compared to the conventional flying capacitor topology, when the number of levels in the inverter output increases. This topology has better fault tolerance, as it is capable of operating with reduced number of levels, in the entire modulation range, in the event of any failure in the H-bridges. The transient as well as the steady state performance of the nine-level version of the proposed topology is experimentally verified in the entire modulation range including the over-modulation region.

Power and delay optimal policies for wireless systems

In this paper we consider a single discrete time queue with infinite buffer. The channel may experience fading. The transmission rate is a linear function of power used for transmission. In this scenario we explicitly obtain power control policies which minimize mean power and/or mean delay. There may also be peak power constraint.

Capture-Induced, Fast, Distributed, Splitting Based Selection with Imperfect Power Control

Opportunistic selection selects the node that improves the overall system performance the most. Selecting the best node is challenging as the nodes are geographically distributed and have only local knowledge. Yet, selection must be fast to allow more time to be spent on data transmission, which exploits the selected node's services. We analyze the impact of imperfect power control on a fast, distributed, splitting based selection scheme that exploits the capture effect by allowing the transmitting nodes to have different target receive powers and uses information about the total received power to speed up selection. Imperfect power control makes the received power deviate from the target and, hence, affects performance. Our analysis quantifies how it changes the selection probability, reduces the selection speed, and leads to the selection of no node or a wrong node. We show that the effect of imperfect power control is primarily driven by the ratio of target receive powers. Furthermore, we quantify its effect on the net system throughput.

A Seventeen-level Inverter With a Single DC-link For Motor Drives

In the present paper, a novel topology for generating a 17-level inverter using three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors. The proposed circuit is analyzed and various aspects of it are presented in the paper. This circuit is experimentally verified and the results are shown. The stability of the capacitor balancing algorithm has been verified during sudden acceleration. This circuit has many pole voltage redundancies. This circuit has an advantage of balancing all the capacitor voltages instantaneously by switching through the redundancies. Another advantage of this topology is its ability to generate all the 17 pole voltages from a single DC link which enables back to back converter operation. Also, the proposed inverter can be operated at all load power factors and modulation indices. Another advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels.

Influence of sputter power on structural and electrical properties of TiO2 films for Al/TiO2/Si gate capacitors

Titanium dioxide (TiO2) thin films were deposited onto p-Si substrates held at room temperature by reactive Direct Current (DC) magnetron sputtering at various sputter powers in the range 80-200W. The as-deposited TiO2 films were annealed at a temperature of 1023K. The post-annealed films were characterized for crystallographic structure, chemical binding configuration, surface morphology and optical absorption. The electrical and dielectric properties of Al/TiO2/p-Si structure were determined from the capacitance-voltage and current-voltage characteristics. X-ray diffraction studies confirmed that the as-deposited films were amorphous in nature. After post-annealing at 1023K, the films formed at lower powers exhibited anatase phase, where as those deposited at sputter powers >160W showed the mixed anatase and rutile phases of TiO2. The surface morphology of the films varied significantly with the increase of sputter power. The electrical and dielectric properties on the air-annealed Al/TiO2/p-Si structures were studied. The effect of sputter power on the electrical and dielectric characteristics of the structure of Al/TiO2/p-Si (metal-insulator-semiconductor) was systematically investigated. Copyright (c) 2014 John Wiley & Sons, Ltd.

Fermi-Edge Transmission Resonance in Graphene Driven by a Single Coulomb Impurity

The interaction between the Fermi sea of conduction electrons and a nonadiabatic attractive impurity potential can lead to a power-law divergence in the tunneling probability of charge through the impurity. The resulting effect, known as the Fermi edge singularity (FES), constitutes one of the most fundamental many-body phenomena in quantum solid state physics. Here we report the first observation of FES for Dirac fermions in graphene driven by isolated Coulomb impurities in the conduction channel. In high-mobility graphene devices on hexagonal boron nitride substrates, the FES manifests in abrupt changes in conductance with a large magnitude approximate to e(2)/h at resonance, indicating total many-body screening of a local Coulomb impurity with fluctuating charge occupancy. Furthermore, we exploit the extreme sensitivity of graphene to individual Coulomb impurities and demonstrate a new defect-spectroscopy tool to investigate strongly correlated phases in graphene in the quantum Hall regime.

DC-Bias-Superposition Characteristics of Ni0.4Zn0.2Mn0.4Fe2O4 Nanopowders Synthesized by Auto-Combustion

Ni0.4Zn0.2Mn0.4Fe2O4 nanopowders were prepared by auto-combustion method. The as-synthesized powders were characterized using X-ray diffraction (XRD) and thermo-gravimetric-differential thermal analysis (TG-DTA), and the powders were densified at different temperatures 400 degrees C, 500 degrees C, 600 degrees C and 700 degrees C/4 hrs using conventional sintering method. The sintered samples were characterized by XRD and transmission electron microscope (TEM). The bulk densities of the samples were increased with an increase of sintering temperature. The grain sizes of all the samples vary in between 18 nm to 30 nm. The hysteresis loops show high saturation magnetization and low coercivity, indicates that it is a soft material. The incremental permeability (permeability with magnetic field superposition) was influenced by both Delta M and H-c. A sample with higher initial permeability and favoured the attainment of a higher incremental permeability. The Q-factor was mainly determined by the sintered density and microstructure. To summarize, a uniform and dense microstructure with relatively small average grain size is favourable for obtaining better dc-bias-superposition characteristics, including permeability and Q-factor.

Timer-Based Distributed Node Selection Scheme Exploiting Power Control and Capture

Opportunistic selection in multi-node wireless systems improves system performance by selecting the ``best'' node and by using it for data transmission. In these systems, each node has a real-valued local metric, which is a measure of its ability to improve system performance. Our goal is to identify the best node, which has the largest metric. We propose, analyze, and optimize a new distributed, yet simple, node selection scheme that combines the timer scheme with power control. In it, each node sets a timer and transmit power level as a function of its metric. The power control is designed such that the best node is captured even if. other nodes simultaneously transmit with it. We develop several structural properties about the optimal metric-to-timer-and-power mapping, which maximizes the probability of selecting the best node. These significantly reduce the computational complexity of finding the optimal mapping and yield valuable insights about it. We show that the proposed scheme is scalable and significantly outperforms the conventional timer scheme. We investigate the effect of. and the number of receive power levels. Furthermore, we find that the practical peak power constraint has a negligible impact on the performance of the scheme.

Low Complexity Power and Scheduling Policies for Wireless Networks to Provide Quality of Service

We consider optimal power allocation policies for a single server, multiuser system. The power is consumed in transmission of data only. The transmission channel may experience multipath fading. We obtain very efficient, low computational complexity algorithms which minimize power and ensure stability of the data queues. We also obtain policies when the users may have mean delay constraints. If the power required is a linear function of rate then we exploit linearity and obtain linear programs with low complexity.

Low-frequency dc bus ripple cancellation in single phase pulse-width modulation inverters

This study presents a topology for a single-phase pulse-width modulation (PWM) converter which achieves low-frequency ripple reduction in the dc bus even when there are grid frequency variations. A hybrid filter is introduced to absorb the low-frequency current ripple in the dc bus. The control strategy for the proposed filter does not require the measurement of the dc bus ripple current. The design criteria for selecting the filter components are also presented in this study. The effectiveness of the proposed circuit has been tested and validated experimentally. A smaller dc-link capacitor is sufficient to keep the low-frequency bus ripple to an acceptable range in the proposed topology.

Secure Transmission in Cooperative Networks with Weak Eavesdroppers

In this letter, we propose a scheme to improve the secrecy rate of cooperative networks using Analog Network Coding (ANC). ANC mixes the signals in the air; the desired signal is then separated out, from the mixed signals, at the legitimate receiver using techniques like self interference subtraction and signal nulling, thereby achieving better secrecy rates. Assuming global channel state information, memoryless adversaries and the decode-and-forward strategy, we seek to maximize the average secrecy rate between the source and the destination, subject to an overall power budget. Then, exploiting the structure of the optimization problem, we compute its optimal solution. Finally, we use numerical evaluations to compare our scheme with the conventional approaches.

Experimental results on low cost microcontroller based DC drive implementation

This paper presents the experimental results for an attractive control scheme implementation using an 8 bit microcontroller. The power converter involved is a 3 phase full controlled bridge rectifier. A single quadrant DC drive has been realized and results have been presented for both open and closed loop implementations.