Estimation of missing data using windowed linear prediction in laterally truncated projection & in cone beam CT

In this paper, we address the reconstruction problem from laterally truncated helical cone-beam projections. The reconstruction problem from lateral truncation, though similar to that of interior radon problem, is slightly different from it as well as the local (lambda) tomography and pseudo-local tomography in the sense that we aim to reconstruct the entire object being scanned from a region-of-interest (ROI) scan data. The method proposed in this paper is a projection data completion approach followed by the use of any standard accurate FBP type reconstruction algorithm. In particular, we explore a windowed linear prediction (WLP) approach for data completion and compare the quality of reconstruction with the linear prediction (LP) technique proposed earlier.

REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures

In this paper we propose the architecture of a SoC fabric onto which applications described in a HLL are synthesized. The fabric is a homogeneous layout of computation, storage and communication resources on silicon. Through a process of composition of resources (as opposed to decomposition of applications), application specific computational structures are defined on the fabric at runtime to realize different modules of the applications in hardware. Applications synthesized on this fabric offers performance comparable to ASICs while retaining the programmability of processing cores. We outline the application synthesis methodology through examples, and compare our results with software implementations on traditional platforms with unbounded resources.

Explicit filtering LES for turbulent non-premixed combustion

Two models for large eddy simulation of turbulent reacting flow in homogeneous turbulence were studied. The sub-grid stress arising out of non-linearities of the Navier-Stokes equations were modeled using an explicit filtering approach. A filtered mass density function (FMDF) approach was used for closure of the sub-grid scalar fluctuations. A posteriori calculations, when compared with the results from the direct numerical simulation, indicate that the explicit filtering is adequate in representing the effect of sub-grid stress on the filtered velocity field in the absence of reaction. Discrepancies arise when reactions occur, but the FMDF approach suffices to account for sub-grid scale fluctuations of the reacting scalars, accurately.

Multi-Mode Phonon-Controlled Field Emission from Carbon Nanotubes: Modeling and Experiments

The main idea proposed in this paper is that in a vertically aligned array of short carbon nanotubes (CNTs) grown on a metal substrate, we consider a frequency dependent electric field, so that the mode-specific propagation of phonons, in correspondence with the strained band structure and the dispersion curves, take place. We perform theoretical calculations to validate this idea with a view of optimizing the field emission behavior of the CNT array. This is the first approach of its kind, and is in contrast to the the conventional approach where a DC bias voltage is applied in order to observe field emission. A first set of experimental results presented in this paper gives a clear indication that phonon-assisted control of field emission current in CNT based thin film diode is possible.

VLSI Implementation of Spatial prediction Based Image Compression Scheme

We propose the design and implementation of hardware architecture for spatial prediction based image compression scheme, which consists of prediction phase and quantization phase. In prediction phase, the hierarchical tree structure obtained from the test image is used to predict every central pixel of an image by its four neighboring pixels. The prediction scheme generates an error image, to which the wavelet/sub-band coding algorithm can be applied to obtain efficient compression. The software model is tested for its performance in terms of entropy, standard deviation. The memory and silicon area constraints play a vital role in the realization of the hardware for hand-held devices. The hardware architecture is constructed for the proposed scheme, which involves the aspects of parallelism in instructions and data. The processor consists of pipelined functional units to obtain the maximum throughput and higher speed of operation. The hardware model is analyzed for performance in terms throughput, speed and power. The results of hardware model indicate that the proposed architecture is suitable for power constrained implementations with higher data rate