Liquid phase epitaxial growth of pure and doped GaSb layers: morphological evolution and native defects

Undoped and Te-doped gallium antimonide (GaSb) layers have been grown on GaSb bulk substrates by the liquid phase epitaxial technique from Ga-rich and Sb-rich melts. The nucleation morphology of the grown layers has been studied as a function of growth temperature and substrate orientation. MOS structures have been fabricated on the epilayers to evaluate the native defect content in the grown layers from the C-V characteristics. Layers grown from antimony rich melts always exhibit p-type conductivity. In contrast, a type conversion from p- to n- was observed in layers grown from gallium rich melts below 400 degrees C. The electron mobility of undoped n-type layers grown from Ga-rich melts and tellurium doped layers grown from Sb- and Ga-rich solutions has been evaluated.

Analysis, Design, Modeling, and Implementation of an Active Clamp HF Link Converter

This paper deals with the system oriented analysis, design, modeling, and implementation of active clamp HF link three phase converter. The main advantage of the topology is reduced size, weight, and cost of the isolation transformer. However, violation of basic power conversion rules due to presence of the leakage inductance in the HF transformer causes over voltage stresses across the cycloconverter devices. It makes use of the snubber circuit necessary in such topologies. The conventional RCD snubbers are dissipative in nature and hence inefficient. The efficiency of the system is greatly improved by using regenerative snubber or active clamp circuit. It consists of an active switching device with an anti-parallel diode and one capacitor to absorb the energy stored in the leakage inductance of the isolation transformer and to regenerate the same without affecting circuit performance. The turn on instant and duration of the active device are selected such that it requires simple commutation requirements. The time domain expressions for circuit dynamics, design criteria of the snubber capacitor with two conflicting constrains (over voltage stress across the devices and the resonating current duration), the simulation results based on generalized circuit model and the experimental results based on laboratory prototype are presented.

Modeling and control of unified power flow controller for transient stability

FACTS controllers are emerging as viable and economic solutions to the problems of large interconnected ne networks, which can endanger the system security. These devices are characterized by their fast response, absence of inertia, and minimum maintenance requirements. Thyristor controlled equipment like Thyristor Controlled Series Capacitor (TCSC), Static Var Compensator (SVC), Thyristor Controlled Phase angle Regulator (TCPR) etc. which involve passive elements result in devices of large sizes with substantial cost and significant labour for installation. An all solid-state device using GTOs leads to reduction in equipment size and has improved performance. The Unified Power Flow Controller (UPFC) is a versatile controller which can be used to control the active and reactive power in the Line independently. The concept of UPFC makes it possible to handle practically all power flow control and transmission line compensation problems, using solid-state controllers, which provide functional flexibility, generally not attainable by conventional thyristor controlled systems. In this paper, we present the development of a control scheme for the series injected voltage of the UPFC to damp the power oscillations and improve transient stability in a power system. (C) 1998 Elsevier Science Ltd. All rights reserved.

Electrochemical studies of polyaniline in a gel polymer electrolyte - High energy and high power characteristics of a solid-state redox supercapacitor

Studies on redox supercapacitors employing electronically conducting polymers are of great importance for hybrid power sources and pulse power applications. In the present study, polyaniline (PANI) has been potentiodynamically deposited on stainless steel substrate and characterized in a gel polymer electrolyte (GPE). Use of the GPE facilitates a voltage limit of the capacitor to 1 V, instead of 0.75 V in aqueous electrolytes. From charge-discharge studies of the solid-state PANI capacitors, a specific capacitance of 250 F g(-1) has been obtained at a specific power of 7.5 kW kg(-1) of PANI. The values of specific capacitance and specific power are considerably higher than those reported in the literature. High energy and high power characteristics of the PANI are presented. (C) 2002 The Electrochemical Society.

Fabrication and evaluation of 450 F electrochemical redox supercapacitors using inexpensive and high-performance, polyaniline coated, stainless-steel electrodes

Redox supercapacitors using polyaniline (PANI) coated. stainless-steel (SS) electrodes have been assembled and characterized. PANI has been deposited on SS substrate by a potentiodynamic method from an acidic electrolyte which contains aniline monomer. By employing stacks of electrodes, each with a geometrical area of 24 cm(2), in acidic perchlorate electrolyte, a capacitance value of about 450 F has been obtained over a long cycle-life. Characterization studies have been carried out by galvanostatic charge-discharge cycling of the capacitors singly, as well as in series and parallel configurations. Various electrical parameters have been evaluated. Use of the capacitors in parallel with a battery for pulse-power loads. and also working of a toy fan connected to the charged capacitors have been demonstrated. A specific capacitance value of about 1300 F g(-1) of PANI has been obtained at a discharge power of about 0.5 kW kg(-1). This value is several times higher than those reported in the literature for PANI and is, perhaps, the highest value known for a capacitor material. The inexpensive SS substrate and the high-capacitance PANI are favorable factors for commercial exploitation. (C) 2002 Elsevier Science B.V. All rights reserved.

Potentiodynamically deposited polyaniline on stainless steel - Inexpensive, high-performance electrodes for electrochemical supercapacitors

Polyaniline (PANI) has been studied as an active material for electrochemical capacitors. Polymerization of aniline to PANI has been carried out potentiodynamically on a stainless steel (SS) substrate, instead of Pt-based substrates generally employed for this application. The PANI/SS electrodes have been evaluated by assembling symmetrical capacitors in NaClO(4) + HClO(4) mixed electrolyte and subjecting them to galvanostatic charge/discharge cycles between 0 and 0.75 V. The effect of substrate has been assessed by comparing the capacitance of PANI/SS and PANI/Pt electrodes. The capacitance of PANI/SS electrode is higher than that of PANI/Pt electrode by several times. The effect of sweep rate of potentiodynamic deposition of PANI/SS on capacitance has been investigated. At a power density of 0.5 kW kg(-1), a capacitance value of 815 F g(-1) of PANI is obtained for the deposition sweep rate of 200 mV s(-1). Increase in thickness of PANI on the SS substrate results in an increase in capacitance of PANI. This value of capacitance is the highest ever reported for any electrochemical capacitor material. Thus, in addition to a favorable economic aspect involved in using SS instead of Pt or Pt-based substrate, the advantage of higher capacitance of PANI has also been achieved. (C) 2002 The Electrochemical Society.

Structural vibration control using resistively shunted piezoceramics

Application of piezoceramic materials in actuation and sensing of vibration is of current interest. Potential and more popular applications of piezoceramics are probably in the field of active vibration control. However, the objective of this work is to investigate the effect of shunted piezoceramics as passive vibration control devices when bonded to a host structure. Resistive shunting of a piezoceramic bonded to a cantilevered duralumin beam has been investigated. The piezoceramic is connected in parallel to an electrical network comprising of resistors and inductors. The piezoceramic is a capacitor that stores and discharges electrical energy that is transformed from the mechanical motion of the structure to which it is bonded. A resistor across the piezoceramic would be termed as a resistively shunted piezoceramic. Similarly, an inductor across the piezoceramic is termed as a resonantly shunted piezoceramic. In this study, the effect of resistive shunting on the nature of damping enhancement to the host structure has been investigated. Analytical studies are presented along with experimental results.

Variable-speed wind power generation using doubly fed wound rotor induction machine - A comparison with alternative schemes

In this paper, a wind energy conversion system (WECS) using grid-connected wound rotor induction machine controlled from the rotor side is compared with both fixed speed and variable speed systems using cage rotor induction machine. The comparison is done on the basis of (I) major hardware components required, (II) operating region, and (III) energy output due to a defined wind function using the characteristics of a practical wind turbine. Although a fixed speed system is more simple and reliable, it severely limits the energy output of a wind turbine. In case of variable speed systems, comparison shows that using a wound rotor induction machine of similar rating can significantly enhance energy capture. This comes about due to the ability to operate with rated torque even at supersynchronous speeds; power is then generated out of the rotor as well as the stator. Moreover, with rotor side control, the voltage rating of the power devices and dc bus capacitor bank is reduced. The size of the line side inductor also decreasesd. Results are presented to show the substantial advantages of the doubly fed system.

Effect of Post-Metallization Hydrogen Annealing on C-V Characteristic of Zirconia Grown Using Atomic Layer Deposition

Substantial amount of fixed charge present in most of the alternative gate dielectrics gives rise to large shifts in the flat-band voltage (VFB) and charge trapping and de-trapping causes hysterectic changes on voltage cycling. Both phenomena affect stable and reliable transistor operation. In this paper we have studied for the first time the effect of post-metallization hydrogen annealing on the C-V curve of MOS capacitors employing zirconia, one of the most promising gate dielectric. Samples were annealed in hydrogen ambient for up to 30 minutes at different temperatures ranging from room temperature to 400°C. C-V measurements were done after annealing at each temperature and the hysteresis width was calculated from the C-V curves. A minimum hysteresis width of ∼35 mV was observed on annealing the sample at 200°C confirming the excellent suitability of this dielectric

Interface states of laser ablated BaTiO3 and Ba0.9Ca0.1TiO3 thin films in MFS structure determined by DLTS and C – V technique

BaTiO3 and Ba0.9Ca0.1TiO3 thin films were deposited on the p – type Si substrate by pulsed excimer laser ablation technique. The Capacitance – Voltage (C-V) measurement measured at 1 MHz exhibited a clockwise rotating hysteresis loop with a wide memory window for the Metal – Ferroelectric – Semiconductor (MFS) capacitor confirming the ferroelectric nature. The low frequency C – V measurements exhibited the response of the minority carriers in the inversion region while at 1 MHz the C – V is of a high frequency type with minimum capacitance in the inversion region. The interface states of both the MFS structures were calculated from the Castagne – Vaipaille method (High – low frequency C – V curve). Deep Level Transient Spectroscopy (DLTS) was used to analyze the interface traps and capture cross section present in the MFS capacitor. There were distinct peaks present in the DLTS spectrum and these peaks were attributed to the presence of the discrete interface states present at the semiconductor – ferroelectric interface. The distribution of calculated interface states were mapped with the silicon energy band gap for both the undoped and Ca doped BaTiO3 thin films using both the C – V and DLTS method. The interface states of the Ca doped BaTiO3 thin films were found to be higher than the pure BaTiO3 thin films.

MFIS and MFS structures using SrBi2Ta2O9 thin films for the FRAM applications

Recently there is an increasing demand and extensive research on high density memories, in particular to the ferroelectric random access memory composed of 1T/1C (1 transistor/1 capacitor) or 2T/2C. FRAM's exhibit fast random acess in read/write mode, non - volatility and low power for good performance. An integration of the ferroelectric on Si is the key importance and in this regard, there had been various models proposed like MFS, MFIS, MFMIS structure etc., Choosing the proper insulator is very essential for the better performance of the device and to exhibit excellent electrical characteristics. ZrTiO4 is a potential candidate because of its excellent thermal stability and lattice match on the Si substrate. SrBi2Ta2O9 and ZrTiO4 thin films were prepared on p - type Si substrate by pulsed excimer laser ablation technique. Optimization of both ZT and SBT thin films in MFS and MFIS structure had been done based on the annealing, oxygen partial pressures and substrate temperatures to have proper texture of the thin films. The dc leakage current, P - E hysteresis, capacitance - voltage and conductance - voltage measurement were carried out. The effect of the frequency dependence on MFIS structure was observed in the C – V curve. It displays a transition of C - V curve from high frequency to low frequency curve on subjection to varied frequencies. Density of interface states has been calculated using Terman and high - low frequency C - V curve. The effect of memory window in the C - V hysteresis were analysed in terms of film thickness and annealing temperatures. DC conduction mechanism were analysed in terms of poole - frenkel, Schottky and space charge limited conduction separately on MFS, MIS structure.

MFIS and MFS structures using SrBi2Ta2O9 thin films for the FRAM applications

Recently there is an increasing demand and extensive research on high density memories, in particular to the ferroelectric random access memory composed of 1T/1C (1 transistor/1 capacitor) or 2T/2C. FRAM's exhibit fast random acess in read/write mode, non - volatility and low power for good performance. An integration of the ferroelectric on Si is the key importance and in this regard, there had been various models proposed like MFS, MFIS, MFMIS structure etc., Choosing the proper insulator is very essential for the better performance of the device and to exhibit excellent electrical characteristics. ZrTiO4 is a potential candidate because of its excellent thermal stability and lattice match on the Si substrate. SrBi2Ta2O9 and ZrTiO4 thin films were prepared on p - type Si substrate by pulsed excimer laser ablation technique. Optimization of both ZT and SBT thin films in MFS and MFIS structure had been done based on the annealing, oxygen partial pressures and substrate temperatures to have proper texture of the thin films. The dc leakage current, P - E hysteresis, capacitance - voltage and conductance - voltage measurement were carried out. The effect of the frequency dependence on MFIS structure was observed in the C – V curve. It displays a transition of C - V curve from high frequency to low frequency curve on subjection to varied frequencies. Density of interface states has been calculated using Terman and high - low frequency C - V curve. The effect of memory window in the C - V hysteresis were analysed in terms of film thickness and annealing temperatures. DC conduction mechanism were analysed in terms of poole - frenkel, Schottky and space charge limited conduction separately on MFS, MIS structure.

Effect of annealing temperature on electrical and nano-structural properties of sol-gel derived ZnO thin films

Zinc oxide (ZnO) thin films have been prepared on silicon substrates by sol-gel spin coating technique with spinning speed of 3,000 rpm. The films were annealed at different temperatures from 200 to 500 A degrees C and found that ZnO films exhibit different nanostructures at different annealing temperatures. The X-ray diffraction (XRD) results showed that the ZnO films convert from amorphous to polycrystalline phase after annealing at 400 A degrees C. The metal oxide semiconductor (MOS) capacitors were fabricated using ZnO films deposited on pre-cleaned silicon (100) substrates and electrical properties such as current versus voltage (I-V) and capacitance versus voltage (C-V) characteristics were studied. The electrical resistivity decreased with increasing annealing temperature. The oxide capacitance was measured at different annealing temperatures and different signal frequencies. The dielectric constant and the loss factor (tan delta) were increased with increase of annealing temperature.

A Low Power Frequency Multiplication Technique for Zigbee Transceiver

A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a given output voltage swing using our technique. The advantages and disadvantages which determine the application areas of the technique are discussed. The issues related to design, layout and process variation are also addressed. Finally, a design is presented for operation in 2.405-2.485-GHz band of ZigBee receiver. SpectreRF simulations show 30% improvement in efficiency for our circuit with regard to conversion of DC bias current to output amplitude, against a LC-VCO. To establish the low-power credentials, we have compared our circuit with an existing technique; our circuit performs better with just 1/3 of total current from supply, and uses one inductor as against three in the latter case. A test chip was implemented in UMC 0.13-mum RF process with spiral on-chip inductors and MIM (metal-insulator-metal) capacitor option.

Extrinsic Analog Synthesis using Piecewise Linear Current-Mode Circuits

A methodology is presented for the synthesis of analog circuits using piecewise linear (PWL) approximations. The function to be synthesized is divided into PWL segments such that each segment can be realized using elementary MOS current-mode programmable-gain circuits. A number of these elementary current-mode circuits when connected in parallel, it is possible to realize piecewise linear approximation of any arbitrary analog function with in the allowed approximation error bounds. Simulation results show a close agreement between the desired function and the synthesized output. The number of PWL segments used for approximation and hence the circuit area is determined by the required accuracy and the smoothness of the resulting function.