From Scarcity to Overload: Finding “Good Enough” Public Information in Myanmar’s Transition Information Symposium Summary Report

The Myanmar Book Aid Preservation Foundation (MBAPF) and Enlightened Research Myanmar (EMR) held an Information Symposium titled, From Scarcity to Overload: Finding “Good Enough” Public Information in Myanmar’s Transition in Yangon, Myanmar on January 28-29, 2016. The Symposium was co-sponsored by the University of Washington’s Henry M. Jackson School of International Studies (JSIS) and the Technology & Social Change Group (TASCHA) of the University’s Information School with support from the United States Agency for International Development (USAID), Microsoft, the Bill & Melinda Gates Foundation, and the Asia Foundation. The Information Symposium was held as part of a larger project supported by USAID, Microsoft, the Bill & Melinda Gates Foundation, and the Tableau Foundation implemented by the University of Washington’s JSIS and TASCHA, along with Myanmar partners, MBAPF and EMR. This project, Information Strategies for Societies in Transition, was developed largely because of the staggering challenges Myanmar is facing as it seeks to “catch-up” in the world’s most economically competitive region.

Informazione quantistica e decoerenza: il caso dei qubit in centri NV

Lo scopo di questa tesi triennale è quello di fornire un'introduzione ad alcuni concetti della computazione quantistica e comprenderne i fenomeni fisici che ne stanno alla base, dall'idea astratta di qubit fino ai più recenti studi sui centri NV, passando attraverso appropriati strumenti matematici. Recentemente si è realizzato che l'uso delle proprietà della meccanica quantistica può migliorare drasticamente le velocità di calcolo. È quindi cresciuto l'interesse nel campo dell'informazione quantistica. Tra le principali difficoltà vi è il fenomeno della decoerenza, responsabile della distruzione degli stati di sovrapposizione quanto-meccanici. Studiamo la dinamica dei sistemi quantistici aperti, soffermandoci sugli aspetti della loro evoluzione rilevanti nel passaggio dal mondo quantico al classico. A tal fine, e per una migliore comprensione della decoerenza, ricaviamo l'equazione master cui deve obbedire la matrice di densità nel noto modello di Jaynes-Cummings per l'interazione ambiente-sistema. In particolare, descriviamo come un ristretto set di manipolazioni sul sistema ci permetta di proteggerlo dalla decoerenza e come tale tecnica, detta disaccoppiamento dinamico, si rivela un utile strumento per la realizzazione di gates quantistici nel caso dei qubit implementati sfruttando i cosiddetti centri NV del diamante.

Logic-Based Delivery of Site-Specifically-Modified Proteins from Gels through Engineered Biomacromolecular Architecture

Thesis (Master's)--University of Washington, 2016-08

Security through Obscurity: Layout Obfuscation of Digital Integrated Circuits using Don't Care Conditions

Contemporary integrated circuits are designed and manufactured in a globalized environment leading to concerns of piracy, overproduction and counterfeiting. One class of techniques to combat these threats is circuit obfuscation which seeks to modify the gate-level (or structural) description of a circuit without affecting its functionality in order to increase the complexity and cost of reverse engineering. Most of the existing circuit obfuscation methods are based on the insertion of additional logic (called “key gates”) or camouflaging existing gates in order to make it difficult for a malicious user to get the complete layout information without extensive computations to determine key-gate values. However, when the netlist or the circuit layout, although camouflaged, is available to the attacker, he/she can use advanced logic analysis and circuit simulation tools and Boolean SAT solvers to reveal the unknown gate-level information without exhaustively trying all the input vectors, thus bringing down the complexity of reverse engineering. To counter this problem, some ‘provably secure’ logic encryption algorithms that emphasize methodical selection of camouflaged gates have been proposed previously in literature [1,2,3]. The contribution of this paper is the creation and simulation of a new layout obfuscation method that uses don't care conditions. We also present proof-of-concept of a new functional or logic obfuscation technique that not only conceals, but modifies the circuit functionality in addition to the gate-level description, and can be implemented automatically during the design process. Our layout obfuscation technique utilizes don’t care conditions (namely, Observability and Satisfiability Don’t Cares) inherent in the circuit to camouflage selected gates and modify sub-circuit functionality while meeting the overall circuit specification. Here, camouflaging or obfuscating a gate means replacing the candidate gate by a 4X1 Multiplexer which can be configured to perform all possible 2-input/ 1-output functions as proposed by Bao et al. [4]. It is important to emphasize that our approach not only obfuscates but alters sub-circuit level functionality in an attempt to make IP piracy difficult. The choice of gates to obfuscate determines the effort required to reverse engineer or brute force the design. As such, we propose a method of camouflaged gate selection based on the intersection of output logic cones. By choosing these candidate gates methodically, the complexity of reverse engineering can be made exponential, thus making it computationally very expensive to determine the true circuit functionality. We propose several heuristic algorithms to maximize the RE complexity based on don’t care based obfuscation and methodical gate selection. Thus, the goal of protecting the design IP from malicious end-users is achieved. It also makes it significantly harder for rogue elements in the supply chain to use, copy or replicate the same design with a different logic. We analyze the reverse engineering complexity by applying our obfuscation algorithm on ISCAS-85 benchmarks. Our experimental results indicate that significant reverse engineering complexity can be achieved at minimal design overhead (average area overhead for the proposed layout obfuscation methods is 5.51% and average delay overhead is about 7.732%). We discuss the strengths and limitations of our approach and suggest directions that may lead to improved logic encryption algorithms in the future. References: [1] R. Chakraborty and S. Bhunia, “HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493–1502, 2009. [2] J. A. Roy, F. Koushanfar, and I. L. Markov, “EPIC: Ending Piracy of Integrated Circuits,” in 2008 Design, Automation and Test in Europe, 2008, pp. 1069–1074. [3] J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, “Security Analysis of Integrated Circuit Camouflaging,” ACM Conference on Computer Communications and Security, 2013. [4] Bao Liu, Wang, B., "Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks,"Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , vol., no., pp.1,6, 24-28 March 2014.

Improving the freshman electrical and computer engineering lab

This thesis covers the challenges of creating and maintaining an introductory engineering laboratory. The history of the University of Illinois Electrical and Computer Engineering department’s introductory course, ECE 110, is recounted. The current state of the course, as of Fall 2008, is discussed along with current challenges arising from the use of a hand-wired prototyping board with logic gates. A plan for overcoming these issues using a new microcontroller-based board with a pseudo hardware description language is discussed. The new microcontroller based system implementation is extensively detailed along with its new accompanying description language. This new system was tried in several sections of the Fall 2008 semester alongside the old system; the students’ final performances with the two different approaches are compared in terms of design, performance, complexity, and enjoyment. The system in its first run shows great promise, increasing the students’ enjoyment, and improving the performance of their designs.

Generating a state t-design by diagonal quantum circuits

We investigate protocols for generating a state t-design by using a fixed separable initial state and a diagonal-unitary t-design in the computational basis, which is a t-design of an ensemble of diagonal unitary matrices with random phases as their eigenvalues. We first show that a diagonal-unitary t-design generates a O (1/2(N))-approximate state t-design, where N is the number of qubits. We then discuss a way of improving the degree of approximation by exploiting non-diagonal gates after applying a diagonal-unitary t-design. We also show that it is necessary and sufficient to use O (log(2)(t)) -qubit gates with random phases to generate a diagonal-unitary t-design by diagonal quantum circuits, and that each multi-qubit diagonal gate can be replaced by a sequence of multi-qubit controlled-phase-type gates with discrete-valued random phases. Finally, we analyze the number of gates for implementing a diagonal-unitary t-design by non-diagonal two- and one-qubit gates. Our results provide a concrete application of diagonal quantum circuits in quantum informational tasks.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.

Quantum Gate and Quantum State Preparation through Neighboring Optimal Control

Successful implementation of fault-tolerant quantum computation on a system of qubits places severe demands on the hardware used to control the many-qubit state. It is known that an accuracy threshold Pa exists for any quantum gate that is to be used for such a computation to be able to continue for an unlimited number of steps. Specifically, the error probability Pe for such a gate must fall below the accuracy threshold: Pe < Pa. Estimates of Pa vary widely, though Pa ∼ 10−4 has emerged as a challenging target for hardware designers. I present a theoretical framework based on neighboring optimal control that takes as input a good quantum gate and returns a new gate with better performance. I illustrate this approach by applying it to a universal set of quantum gates produced using non-adiabatic rapid passage. Performance improvements are substantial comparing to the original (unimproved) gates, both for ideal and non-ideal controls. Under suitable conditions detailed below, all gate error probabilities fall by 1 to 4 orders of magnitude below the target threshold of 10−4. After applying the neighboring optimal control theory to improve the performance of quantum gates in a universal set, I further apply the general control theory in a two-step procedure for fault-tolerant logical state preparation, and I illustrate this procedure by preparing a logical Bell state fault-tolerantly. The two-step preparation procedure is as follow: Step 1 provides a one-shot procedure using neighboring optimal control theory to prepare a physical qubit state which is a high-fidelity approximation to the Bell state |β01⟩ = 1/√2(|01⟩ + |10⟩). I show that for ideal (non-ideal) control, an approximate |β01⟩ state could be prepared with error probability ϵ ∼ 10−6 (10−5) with one-shot local operations. Step 2 then takes a block of p pairs of physical qubits, each prepared in |β01⟩ state using Step 1, and fault-tolerantly prepares the logical Bell state for the C4 quantum error detection code.

Faulkner revisited : narrating property, race, gender and history in William Faulkner's Go Down, Moses, Toni Morrison's Song of Solomon and Gloria Naylor's Mama Day

My thesis explores the formation of the subject in the novels of Faulkner’s Go Down, Moses, Toni Morrison’s Song of Solomon, and Gloria Naylor’s Mama Day. I attach the concept of property in terms of how male protagonists are obsessed with materialistic ownership and with the subordination of women who, as properties, consolidate their manhood. The three novelists despite their racial, gendered, and literary differences share the view that identity and truth are mere social and cultural constructs. I incorporate the work of Judith Butler and other poststructuralist figures, who see identity as a matter of performance rather than a natural entity. My thesis explores the theme of freedom, which I attached to the ways characters use their bodies either to confine or to emancipate themselves from the restricting world of race, class, and gender. The three novelists deconstruct any system of belief that promulgates the objectivity of truth in historical documents. History in the three novels, as with the protagonists, perception of identity, remains a social construct laden with distortions to serve particular political or ideological agendas. My thesis gives voice to African American female characters who are associated with love and racial and gender resistance. They become the reservoirs of the African American legacy in terms of their association with the oral and intuitionist mode of knowing, which subverts the male characters’ obsession with property and with the mainstream empiricist world. In this dissertation, I use the concept of hybridity as a literary and theoretical devise that African-American writers employ. In effect, I embark on the postcolonial studies of Henry Louise Gates, Paul Gilroy, W. E. B Du Bois, James Clifford, and Arjun Appadurai in order to reflect upon the fluidity of Morrison’s and Naylor’s works. I show how these two novelists subvert Faulkner’s essentialist perception of truth, and of racial and gendered identity. They associate the myth of the Flying African with the notion of hybridity by making their male protagonists criss-cross Northern and Southern regions. I refer to Mae Gwendolyn Henderson’s article on “Speaking in Tongues” in my analysis of how Naylor subverts the patriarchal text of both Faulkner and Morrison in embarking on a more feminine version of the flying African, which she relates to an ex-slave, Sapphira Wade, a volatile female character who resists fixed claim over her story and identity. In dealing with the concept of hybridity, I show that Naylor rewrites both authors’ South by making Willow Springs a more fluid space, an assumption that unsettles the scores of critics who associate the island with authenticity and exclusive rootedness.

Vazão em soleiras controladas ou não por comportas

Os controladores de caudal, normalmente implementados em sistemas Supervisory control and data acquisition (SCADA), apresentam uma grande relevância no controlo automático de canais de adução. Para garantir que os controladores de caudal sejam fiáveis em todo o seu domínio de funcionamento (em situações de escoamento com ressalto livre ou submerso e de transição entre escoamentos com ressalto livre e ressalto submerso) foram comparados os resultados dos ensaios experimentais com diferentes métodos de cálculo da vazão em comportas e/ou sobre soleiras. O programa de ensaios foi realizado nos canais laboratorial e experimental da Universidade de Évora. Foram realizados ensaios em comportas planas verticais e em soleiras do tipo Waterways Experiment Station (WES) controladas ou não por comportas planas verticais. Em ambos os casos, foram contempladas as situações de escoamento com ressalto livre e submerso. Os resultados obtidos mostram que: a) para as comportas, o método Rajaratnam e Subramanya (1967a) conduz a bons resultados com um erro percentual médio absoluto MAPE < 1% para o escoamento com ressalto livre e MAPE < 4% para o submerso; a transição entre escoamentos foi identificada corretamente por este método; b) para as soleiras, obtiveram-se bons resultados para o escoamento com ressalto livre para o método USACE (1987), com MAPE < 2%, e para o submerso através do método Alves e Martins (2011), com MAPE < 5%; a transição entre escoamentos pode ser considerada adequada de acordo com a curva experimental de Grace (1963); c) para soleiras controladas por comporta, conseguiram-se bons resultados para o escoamento com ressalto livre recorrendo à equação dos orifícios de pequenas dimensões, com MAPE < 1, 5%, e para o submerso com a equação dos orifícios totalmente submersos com MAPE < 1, 6%; em ambos os casos foi necessária calibração do coeficiente de vazão; a transição entre escoamentos foi adequada pelo método de Grace (1963). Com base nos resultados obtidos, foi possível definir um algoritmo de vazão generalizado para comportas e/ou soleiras que permite a determinação da vazão para as situações de escoamento com ressalto livre e submerso incluindo a transição entre escoamentos; ABSTRACT: Flow controllers, usually implemented in Supervisory Control and Data Acquisition (SCADA) systems, are very important in the automatic control of irrigation canal systems. To ensure that flow controllers are reliable for the entire operating range (free or submerged flow and flow transitions) the experimental results were compared with different methods of flow measurement for gates and/or weirs. The test program was conducted in the laboratory flume and in the automatic canal of the University of ´Evora. Tests were carried in sluice gates and in broad-crested weirs controlled or not by sluice gate. In both cases free and submerged flow conditions were analyzed. The results show that: a) for the sluice gates, the method of Rajaratnam e Subramanya (1967a) leads to good results with a mean absolute percentage error (MAPE) < 1% for free flow and MAPE < 4% for submerged flow. The transition between flows is correctly identified by this method; b) for the uncontrolled weir, good results were obtained for free flow with the method USACE (1987) with MAPE < 2%, and for submerged flow by the method Alves e Martins (2011) with MAPE < 5%. The transition between flows can be accurately defined by the experimental curve of Grace (1963); c) for the controlled weir, good results were achieved for the free flow with the small orifice equation with MAPE < 1.5% and for submerged flow with the submerged orifice equation with MAPE < 1.6%; in both cases the calibration of the discharge coefficient is needed. The transition between flows can be accomplished through Grace (1963) method. Based on the obtained results, it was possible to define a generalized flow algorithm for gates and/or weirs that allows flow determination for free and submerged flow conditions including the transition between flows.

Physical Design Methodologies for Low Power and Reliable 3D ICs

As the semiconductor industry struggles to maintain its momentum down the path following the Moore's Law, three dimensional integrated circuit (3D IC) technology has emerged as a promising solution to achieve higher integration density, better performance, and lower power consumption. However, despite its significant improvement in electrical performance, 3D IC presents several serious physical design challenges. In this dissertation, we investigate physical design methodologies for 3D ICs with primary focus on two areas: low power 3D clock tree design, and reliability degradation modeling and management. Clock trees are essential parts for digital system which dissipate a large amount of power due to high capacitive loads. The majority of existing 3D clock tree designs focus on minimizing the total wire length, which produces sub-optimal results for power optimization. In this dissertation, we formulate a 3D clock tree design flow which directly optimizes for clock power. Besides, we also investigate the design methodology for clock gating a 3D clock tree, which uses shutdown gates to selectively turn off unnecessary clock activities. Different from the common assumption in 2D ICs that shutdown gates are cheap thus can be applied at every clock node, shutdown gates in 3D ICs introduce additional control TSVs, which compete with clock TSVs for placement resources. We explore the design methodologies to produce the optimal allocation and placement for clock and control TSVs so that the clock power is minimized. We show that the proposed synthesis flow saves significant clock power while accounting for available TSV placement area. Vertical integration also brings new reliability challenges including TSV's electromigration (EM) and several other reliability loss mechanisms caused by TSV-induced stress. These reliability loss models involve complex inter-dependencies between electrical and thermal conditions, which have not been investigated in the past. In this dissertation we set up an electrical/thermal/reliability co-simulation framework to capture the transient of reliability loss in 3D ICs. We further derive and validate an analytical reliability objective function that can be integrated into the 3D placement design flow. The reliability aware placement scheme enables co-design and co-optimization of both the electrical and reliability property, thus improves both the circuit's performance and its lifetime. Our electrical/reliability co-design scheme avoids unnecessary design cycles or application of ad-hoc fixes that lead to sub-optimal performance. Vertical integration also enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. In addition, a dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPU's operating points to adjust DRAM's voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAM's resilience without sacrificing performance. The proposed physical design methodologies should act as important building blocks for 3D ICs and push 3D ICs toward mainstream acceptance in the near future.

Lugares de fronteira: as tascas localizadas nas portas da muralha Fernandina de Évora

Esta dissertação de mestrado tem por objecto de estudo o conjunto das tascas localizadas nas portas da Muralha Fernandina de Évora. Praticamente desaparecidos espaços ainda íntegros, pode-se considerar que estas construções integram uma rede de estabelecimentos composta por estruturas militares, religiosas, de lazer e de carácter colectivo, que se encontram associadas e caracterizam as portas medievais de Évora. O objectivo desta investigação é o estudo urbanístico e arquitectónico das portas urbanas, e o modo como os estabelecimentos de venda de bebida configuraram as diversas narrativas urbanas a partir de diferentes orientações políticas ao longo dos tempos. O caso de Évora é tomado como base de trabalho por ser legível ainda uma imagem de conjunto, a partir de vestígios, exemplares minimamente conservados, fontes históricas, impressas e fotográficas. A articulação urbana típica e recorrente, na relação directa tasca-porta, pode-se encontrar noutras cidades alentejanas, e nas cidades amuralhadas em geral; PLACES OF FRONTIER: THE TAVERNS LOCATED IN THE GATES OF EVORA'S FERNANDINA WALL ABSTRACT: This dissertation has as subject the study of the taverns located in the gates of Évora's Fernandina Wall. Despite the almost disappearance of intact spaces, it can be considered that these buildings are part of a network of institutions composed of various structures such as military, religious, recreational and collective character, which are associated and feature the ancient medieval gates of Évora. The aim of this investigation is the urban and architectural study of the urban gates, and how the beverage outlets have represented the various urban narratives from different political orientations over time. The case of Évora is the base of work by being a readable group, from traces, minimally preserved specimens, historical, printed and photographic sources. The typical and recurrent urban articulation, in a direct relation tavern-gate, can be seen in other Alentejo towns, and walled cities in general.

Sumpter Prison, Andersonville, Georgia, June 1864 /

Shows the prison with wooden fence, 18 guard towers, the famous "deadline," the north and south gates, Sweetwater Creek, "Valley of Death," fortification, batteries, and cook house. He depicts overcrowding by a blizzard of tiny dots everywhere, writing the dots stand for "Union soldiers."

Studio e sviluppo di un simulatore ed ottimizzatore di traiettoria per aerei da competizione

L'obbiettivo principale di questa tesi è la creazione di un particolare strumento capace di calcolare, dati in input le coordinate geografiche in latitudine e longitudine dei vari gates di passaggio del velivolo e delle caratteristiche principali di quest'ultimo, la traiettoria ottimale, ovvero la più veloce, restando pur sempre nei limiti strutturali e in quelli stabiliti dal regolamento, oltre che ad una serie di valori utili per effettuare tale percorso, quali la variazione di potenza, di coefficiente di portanza, di velocità, ecc. Dopo una prima fase di raccolta delle informazioni (regolamento della competizione, dati tecnici dei velivoli usati, del motore e dell'elica) ne è seguita una seconda in cui, partendo dall'analisi dei risultati ottenuti da un precedente tool di calcolo in Excel, si è provveduto a scriverne uno nuovo operante in ambiente MatLab.

The Relationship of Culturally Responsive Instruction and the Reading Comprehension and Attitude of Struggling Urban Adolescent Readers

Culturally responsive instruction refers to the identification of relevant cultural aspects of students’ lives and infusion of these into the curriculum. This instructional approach assumes that a culturally appropriate curriculum can potentially motivate, engage, and lead students to higher rates of achievement. This quasi-experimental study (N=44) investigated the relationship of culturally responsive instruction and the reading comprehension and attitude of struggling urban adolescent readers. The study incorporated the use of culturally responsive instruction using culturally relevant literature (CRL), the Bluford Series Novels, as authentic texts of instruction. Participants were seventh grade reading students at a Title I middle school in South Florida. After a baseline period, two different classes were taught for 8 weeks using different methods. One class formed the experimental group (n=22) and the other class formed the comparison group (n=22). The CRI curriculum for the experimental group embraced the socio-cultural perspective through the use of small discussion groups in which students read and constructed meaning with peers through interaction with the Bluford Series Novels; gave written responses to multiple strategies according to SCRAP – Summarize, Connect, Reflect, Ask Questions, Predict; responded to literal and inferential questions, while at the same time validating their responses through evidence from the text. The Read XL (basal reader) curriculum of the comparison group utilized a traditional form of instruction which incorporated the reading of passages followed by responses to comprehension questions, and teacher-led whole group discussion. The main sources of data were collected from the Gates-MacGinitie Reading Tests, the Florida Assessments for Instruction in Reading (FAIR), and the Rhody Secondary Reading Attitude Assessment. Statistical analyses were performed using Repeated Measures ANOVAs. Findings from the study revealed that the experimental participants’ reading attitudes and FAIR comprehension scores increased when compared to the comparison group. Overall, the results from the study revealed that culturally responsive instruction can potentially foster reading comprehension and a more positive attitude towards reading. However, a replication of this study in other settings with a larger, more randomized sample size and a greater ethnic variation is needed in order to make full generalizations.