Ordered gan/ingan nanorods arrays grown by molecular beam epitaxy for phosphor-free white light emission

The basics of the self-assembled growth of GaN nanorods on Si(111) are reviewed. Morphology differences and optical properties are compared to those of GaN layers grown directly on Si(111). The effects of the growth temperature on the In incorporation in self-assembled InGaN nanorods grown on Si(111) is described. In addition, the inclusion of InGaN quantum disk structures into selfassembled GaN nanorods show clear confinement effects as a function of the quantum disk thickness. In order to overcome the properties dispersion and the intrinsic inhomogeneous nature of the self-assembled growth, the selective area growth of GaN nanorods on both, c-plane and a-plane GaN on sapphire templates, is addressed, with special emphasis on optical quality and morphology differences. The analysis of the optical emission from a single InGaN quantum disk is shown for both polar and non-polar nanorod orientations

MIA - a free and open source software for gray scale medical image analysis

Background Gray scale images make the bulk of data in bio-medical image analysis, and hence, the main focus of many image processing tasks lies in the processing of these monochrome images. With ever improving acquisition devices, spatial and temporal image resolution increases, and data sets become very large. Various image processing frameworks exists that make the development of new algorithms easy by using high level programming languages or visual programming. These frameworks are also accessable to researchers that have no background or little in software development because they take care of otherwise complex tasks. Specifically, the management of working memory is taken care of automatically, usually at the price of requiring more it. As a result, processing large data sets with these tools becomes increasingly difficult on work station class computers. One alternative to using these high level processing tools is the development of new algorithms in a languages like C++, that gives the developer full control over how memory is handled, but the resulting workflow for the prototyping of new algorithms is rather time intensive, and also not appropriate for a researcher with little or no knowledge in software development. Another alternative is in using command line tools that run image processing tasks, use the hard disk to store intermediate results, and provide automation by using shell scripts. Although not as convenient as, e.g. visual programming, this approach is still accessable to researchers without a background in computer science. However, only few tools exist that provide this kind of processing interface, they are usually quite task specific, and don’t provide an clear approach when one wants to shape a new command line tool from a prototype shell script. Results The proposed framework, MIA, provides a combination of command line tools, plug-ins, and libraries that make it possible to run image processing tasks interactively in a command shell and to prototype by using the according shell scripting language. Since the hard disk becomes the temporal storage memory management is usually a non-issue in the prototyping phase. By using string-based descriptions for filters, optimizers, and the likes, the transition from shell scripts to full fledged programs implemented in C++ is also made easy. In addition, its design based on atomic plug-ins and single tasks command line tools makes it easy to extend MIA, usually without the requirement to touch or recompile existing code. Conclusion In this article, we describe the general design of MIA, a general purpouse framework for gray scale image processing. We demonstrated the applicability of the software with example applications from three different research scenarios, namely motion compensation in myocardial perfusion imaging, the processing of high resolution image data that arises in virtual anthropology, and retrospective analysis of treatment outcome in orthognathic surgery. With MIA prototyping algorithms by using shell scripts that combine small, single-task command line tools is a viable alternative to the use of high level languages, an approach that is especially useful when large data sets need to be processed.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

Soft solution fluorine-free synthesis of anatase nanoparticles with tailored morphology

TiO2 nanoparticles with tailored morphology have been synthesized under exceptionally soft conditions. The strategy is based on the use of a non-aqueous alcoholic reaction medium in which water traces, coming either from the air (atmospheric water) or from an ethanol–water azeotropic mixture (ethanol 96%), are incorporated in order to accelerate hydrolysis of the Ti–precursor. Moreover, organic surfactants have been used as capping agents so as to tailor crystal growth in certain preferential directions. Combinations of oleic acid and oleylamine, which lead to the formation of another surfactant, dioleamide, are employed instead of fluorine-based compounds, thus increasing the sustainability of the process. As a result, TiO2 nanostructured hierarchical microspheres and individual nanoparticles with exposed high-energy facets can be obtained at atmospheric pressure and temperatures as low as 78 °C.

SONIA REGINA PRADO

A dissertação teve como objetivo principal estudar como uma Instituição de Ensino Superior Privada (IES) atuante no Brasil tem crescido pós Lei de Diretrizes e Bases (LDB) de 1996 até 2015, por meio da análise do curso de bacharelado em Administração de Empresas, nas modalidades: presencial, EAD e Flex (semipresencial). Para este fim, foi realizada uma pesquisa exploratória, de caráter qualitativo baseada no método do estudo de caso. Para coleta de evidências foram analisados relatórios corporativos (Annual Report, Relatórios Internos e outros documentos), entrevistas baseadas em roteiro semiestruturado com gestores da IES privada e observações. Dentre os principais achados, verificou-se que as principais estratégicas de crescimento da IES privada estudada se basearam em fusões e aquisições de outras IES, abertura de novos polos de EAD, na abertura de novas unidades próprias, bem como em inovações em várias dimensões da organização. Os programas governamentais de financiamento aos alunos também são fortes contribuintes para este crescimento, como o Fundo de Financiamento ao Estudante do Ensino Superior (FIES) e o Programa Universidade para Todos (Prouni). Com essa nova realidade, o ensino superior privado recebeu incentivo e facilitação para o seu crescimento, a um ritmo acelerado. Consequentemente pode-se concluir que a IES privada estudada adotou as seguintes estratégias de crescimento: Expansão orgânica com fusões/ aquisições de Instituições menores, com desenvolvimento de planos para todos os campi Brasil; Greenfield (por meio de solicitação de autorização de novas unidades e/ou cursos) em cidades sem possibilidades de aquisições/fusões, e aumentando o número de vagas/ matriculas nas unidades já existentes, aderiu aos programas do governo e também cuidou da evasão por meio de: Seguro educacional; gestão preparada para atender necessidades do discente; Sistema de Ensino com currículos integrados nacionalmente; Intercâmbio de alunos e professores entre as diversas unidades em todas as regiões do país e padronização dos processos.

Two sterol regulatory element-like sequences mediate up-regulation of caveolin gene transcription in response to low density lipoprotein free cholesterol

Caveolae form the terminus for a major pathway of intracellular free cholesterol (FC) transport. Caveolin mRNA levels in confluent human skin fibroblasts were up-regulated following increased uptake of low density lipoprotein (LDL) FC. The increase induced by FC was not associated with detectable change in mRNA stability, indicating that caveolin mRNA levels were mediated at the level of gene transcription. A total of 924 bp of 5′ flanking region of the caveolin gene were cloned and sequenced. The promoter sequence included three G+C-rich potential sterol regulatory elements (SREs), a CAAT sequence and a Sp1 consensus sequence. Deletional mutagenesis of individual SRE-like sequences indicated that of these two (at −646 and −395 bp) were essential for the increased transcription rates mediated by LDL-FC, whereas the third was inconsequential. Gel shift analysis of protein binding from nuclear extracts to these caveolin promoter DNA sequences, together with DNase I footprinting, confirmed nucleoprotein binding to the SRE-like elements as part of the transcriptional response to LDL-FC. A supershift obtained with antibody to SRE-binding protein 1 (SPEBP-1) indicated that this protein binds at −395 bp. There was no reaction at −395 bp with anti-Sp1 antibody nor with either antibody at −646 bp. The cysteine protease inhibitor N-acetyl-leu-leu-norleucinal (ALLN), which inhibits SREBP catabolism, superinhibited caveolin mRNA levels regardless of LDL-FC. This finding suggests that SREBP inhibits caveolin gene transcription in contrast to its stimulating effect on other promoters. The findings of this study are consistent with the postulated role for caveolin as a regulator of cellular FC homeostasis in quiescent peripheral cells, and the coordinate regulation by SREBP of FC influx and efflux.

Testosterone Signaling through Internalizable Surface Receptors in Androgen Receptor-free Macrophages

Testosterone acts on cells through intracellular transcription-regulating androgen receptors (ARs). Here, we show that mouse IC-21 macrophages lack the classical AR yet exhibit specific nongenomic responses to testosterone. These manifest themselves as testosterone-induced rapid increase in intracellular free [Ca2+], which is due to release of Ca2+ from intracellular Ca2+ stores. This Ca2+ mobilization is also inducible by plasma membrane-impermeable testosterone-BSA. It is not affected by the AR blockers cyproterone and flutamide, whereas it is completely inhibited by the phospholipase C inhibitor U-73122 and pertussis toxin. Binding sites for testosterone are detectable on the surface of intact IC-21 cells, which become selectively internalized independent on caveolae and clathrin-coated vesicles upon agonist stimulation. Internalization is dependent on temperature, ATP, cytoskeletal elements, phospholipase C, and G-proteins. Collectively, our data provide evidence for the existence of G-protein-coupled, agonist-sequestrable receptors for testosterone in plasma membranes, which initiate a transcription-independent signaling pathway of testosterone.

Blood glutathione synthesis rates in healthy adults receiving a sulfur amino acid-free diet

The availability of cysteine is thought to be the rate limiting factor for synthesis of the tripeptide glutathione (GSH), based on studies in rodents. GSH status is compromised in various disease states and by certain medications leading to increased morbidity and poor survival. To determine the possible importance of dietary cyst(e)ine availability for whole blood glutathione synthesis in humans, we developed a convenient mass spectrometric method for measurement of the isotopic enrichment of intact GSH and then applied it in a controlled metabolic study. Seven healthy male subjects received during two separate 10-day periods an l-amino acid based diet supplying an adequate amino acid intake or a sulfur amino acid (SAA) (methionine and cysteine) free mixture (SAA-free). On day 10, l-[1-13C]cysteine was given as a primed, constant i.v. infusion (3μmol⋅kg−1⋅h−1) for 6 h, and incorporation of label into whole blood GSH determined by GC/MS selected ion monitoring. The fractional synthesis rate (mean ± SD; day-1) of whole blood GSH was 0.65 ± 0.13 for the adequate diet and 0.49 ± 0.13 for the SAA-free diet (P < 0.01). Whole blood GSH was 1,142 ± 243 and 1,216 ± 162 μM for the adequate and SAA-free periods (P > 0.05), and the absolute rate of GSH synthesis was 747 ± 216 and 579 ± 135 μmol⋅liter−1⋅day−1, respectively (P < 0.05). Thus, a restricted dietary supply of SAA slows the rate of whole blood GSH synthesis and diminishes turnover, with maintenance of the GSH concentration in healthy subjects.

Equilibrium constants and free energies in unfolding of proteins in urea solutions

A novel thermodynamic approach to the reversible unfolding of proteins in aqueous urea solutions has been developed based on the premise that urea ligands are bound cooperatively to the macromolecule. When successive stoichiometric binding constants have values larger than expected from statistical effects, an equation for moles of bound urea can be derived that contains imaginary terms. For a very steep unfolding curve, one can then show that the fraction of protein unfolded, B̄, depends on the square of the urea concentration, U, and is given by \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \setlength{\oddsidemargin}{-69pt} \begin{document} \begin{equation*}\bar {B}=\frac{{\mathit{A}}^{{\mathit{2}}}_{{\mathit{1}}}{\mathit{e}}^{{\mathrm{{\lambda}}}n\bar {B}}{\mathit{U}}^{{\mathit{2}}}}{{\mathrm{1\hspace{.167em}+\hspace{.167em}}}{\mathit{A}}^{{\mathrm{2}}}_{{\mathrm{1}}}{\mathit{e}}^{{\mathrm{{\lambda}}}\bar {B}}{\mathit{U}}^{{\mathrm{2}}}}{\mathrm{.}}\end{equation*}\end{document} A12 is the binding constant as B̄→ 0, and λ is a parameter that reflects the augmentation in affinities of protein for urea as the moles bound increases to the saturation number, n. This equation provides an analytic expression that reproduces the unfolding curve with good precision, suggests a simple linear graphical procedure for evaluating A12 and λ, and leads to the appropriate standard free energy changes. The calculated ΔG° values reflect the coupling of urea binding with unfolding of the protein. Some possible implications of this analysis to protein folding in vivo are described.

Binding site of brefeldin A at the interface between the small G protein ADP-ribosylation factor 1 (ARF1) and the nucleotide-exchange factor Sec7 domain

Sec7 domains (Sec7d) catalyze the exchange of guanine nucleotide on ARFs. Recent studies indicated that brefeldin A (BFA) inhibits Sec7d-catalyzed nucleotide exchange on ARF1 in an uncompetitive manner by trapping an early intermediate of the reaction: a complex between GDP-bound ARF1 and Sec7d. Using 3H-labeled BFA, we show that BFA binds to neither isolated Sec7d nor isolated ARF1–GDP, but binds to the transitory Sec7d–ARF1–GDP complex and stabilizes it. Two pairs of residues at positions 190–191 and 198–208 (Arno numbering) in Sec7d contribute equally to the stability of BFA binding, which is also sensitive to mutation of H80 in ARF1. The catalytic glutamic (E156) residue of Sec7d is not necessary for BFA binding. In contrast, BFA does not bind to the intermediate catalytic complex between nucleotide-free ARF1 and Sec7d. These results suggest that, on initial docking steps between ARF1–GDP and Sec7d, BFA inserts like a wedge between the switch II region of ARF1–GDP and a surface encompassing residues 190–208, at the border of the characteristic hydrophobic groove of Sec7d. Bound BFA would prevent the switch regions of ARF1–GDP from reorganizing and forming tighter contacts with Sec7d and thereby would maintain the bound GDP of ARF1 at a distance from the catalytic glutamic finger of Sec7d.

The negative feedback actions of progesterone on gonadotropinreleasing hormone secretion are transduced by the classical progesterone receptor

Progesterone (P) powerfully inhibits gonadotropin-releasing hormone (GnRH) secretion in ewes, as in other species, but the neural mechanisms underlying this effect remain poorly understood. Using an estrogen (E)-free ovine model, we investigated the immediate GnRH and luteinizing hormone (LH) response to acute manipulations of circulating P concentrations and whether this response was mediated by the nuclear P receptor. Simultaneous hypophyseal portal and jugular blood samples were collected over 36 hr: 0–12 hr, in the presence of exogenous P (P treatment begun 8 days earlier); 12–24 hr, P implant removed; 24–36 hr, P implant reinserted. P removal caused a significant rapid increase in the GnRH pulse frequency, which was detectable within two pulses (175 min). P insertion suppressed the GnRH pulse frequency even faster: the effect detectable within one pulse (49 min). LH pulsatility was modulated identically. The next two experiments demonstrated that these effects of P are mediated by the nuclear P receptor since intracerebroventricularly infused P suppressed LH release but 3α-hydroxy-5α-pregnan-20-one, which operates through the type A γ-aminobutyric acid receptor, was without effect and pretreatment with the P-receptor antagonist RU486 blocked the ability of P to inhibit LH. Our final study showed that P exerts its acute suppression of GnRH through an E-dependent system because the effects of P on LH secretion, lost after long-term E deprivation, are restored after 2 weeks of E treatment. Thus we demonstrate that P acutely inhibits GnRH through an E-dependent nuclear P-receptor system.

Mode matches and their locations in the hydrophobic free energy sequences of peptide ligands and their receptor eigenfunctions

Patterns in sequences of amino acid hydrophobic free energies predict secondary structures in proteins. In protein folding, matches in hydrophobic free energy statistical wavelengths appear to contribute to selective aggregation of secondary structures in “hydrophobic zippers.” In a similar setting, the use of Fourier analysis to characterize the dominant statistical wavelengths of peptide ligands’ and receptor proteins’ hydrophobic modes to predict such matches has been limited by the aliasing and end effects of short peptide lengths, as well as the broad-band, mode multiplicity of many of their frequency (power) spectra. In addition, the sequence locations of the matching modes are lost in this transformation. We make new use of three techniques to address these difficulties: (i) eigenfunction construction from the linear decomposition of the lagged covariance matrices of the ligands and receptors as hydrophobic free energy sequences; (ii) maximum entropy, complex poles power spectra, which select the dominant modes of the hydrophobic free energy sequences or their eigenfunctions; and (iii) discrete, best bases, trigonometric wavelet transformations, which confirm the dominant spectral frequencies of the eigenfunctions and locate them as (absolute valued) moduli in the peptide or receptor sequence. The leading eigenfunction of the covariance matrix of a transmembrane receptor sequence locates the same transmembrane segments seen in n-block-averaged hydropathy plots while leaving the remaining hydrophobic modes unsmoothed and available for further analyses as secondary eigenfunctions. In these receptor eigenfunctions, we find a set of statistical wavelength matches between peptide ligands and their G-protein and tyrosine kinase coupled receptors, ranging across examples from 13.10 amino acids in acid fibroblast growth factor to 2.18 residues in corticotropin releasing factor. We find that the wavelet-located receptor modes in the extracellular loops are compatible with studies of receptor chimeric exchanges and point mutations. A nonbinding corticotropin-releasing factor receptor mutant is shown to have lost the signatory mode common to the normal receptor and its ligand. Hydrophobic free energy eigenfunctions and their transformations offer new quantitative physical homologies in database searches for peptide-receptor matches.

Systematic review of dietary intervention trials to lower blood total cholesterol in free-living subjects

Objectives: To estimate the efficacy of dietary advice to lower blood total cholesterol concentration in free-living subjects and to investigate the efficacy of different dietary recommendations.

Transcriptional activation by hepatocyte nuclear factor-4 in a cell-free system derived from rat liver nuclei

Hepatocyte nuclear factor-4 (HNF4) regulates gene expression by binding to direct repeat motifs of the RG(G/T)TCA sequence separated by one nucleotide (DR1). In this study we demonstrate that endogenous HNF4 present in rat liver nuclear extracts, as well as purified recombinant HNF4, activates transcription from naked DNA templates containing multiple copies of the DR1 element linked to the adenovirus major late promoter. Recombinant HNF4 also activates transcription from the rat cellular retinol binding protein II (CRBPII) promoter in vitro. The region between –105 and –63 bp of this promoter is essential for HNF-mediated transactivation. The addition of a peptide containing the LXXLL motif abolished HNF4-mediated transactivation in vitro suggesting that LXXLL-containing protein factor(s) are involved in HNF4-mediated transactivation in rat liver nuclear extracts. This is the first report on transactivation by HNF4 in a cell-free system derived from rat liver nuclei.

Escherichia coli strains that allow antibiotic-free plasmid selection and maintenance by repressor titration

We report the construction of two novel Escherichia coli strains (DH1lacdapD and DH1lacP2dapD) that facilitate the antibiotic-free selection and stable maintenance of recombinant plasmids in complex media. They contain the essential chromosomal gene, dapD, under the control of the lac operator/promoter. Unless supplemented with IPTG (which induces expression of dapD) or DAP, these cells lyse. However, when the strains are transformed with a multicopy plasmid containing the lac operator, the operator competitively titrates the LacI repressor and allows expression of dapD from the lac promoter. Thus transformants can be isolated and propagated simply by their ability to grow on any medium by repressor titration selection. No antibiotic resistance genes or other protein expressing sequences are required on the plasmid, and antibiotics are not necessary for plasmid selection, making these strains a valuable tool for therapeutic DNA and recombinant protein production. We describe the construction of these strains and demonstrate plasmid selection and maintenance by repressor titration, using the new pORT plasmid vectors designed to facilitate recombinant DNA exploitation.