Comment on "From geodesics of the multipole solutions to the perturbed Kepler problem"

In this Comment we explain the discrepancies mentioned by the authors between their results and ours about the in?uence of the gravitational quadrupole moment in the perturbative calculation of corrections to the precession of the periastron of quasielliptical Keplerian equatorial orbits around a point mass. The discrepancy appears to be a consequence of two different calculations of the angular momentum of the orbits.

Growth response to ozone of annual species from Mediterranean pastures

Ozone (O3) phytotoxicity has been reported on a wide range of plant species. However, scarce information has been provided regarding the sensitivity of semi-natural grassland species, especially those from dehesa Mediterranean grasslands, in spite of their great biological diversity and the high O3 levels recorded in the region. A screening study was carried out in open-top chambers (OTCs) to assess the O3-sensitivity of representative therophytes of these ecosystems based on the response of selected growth-related parameters. Three O3 treatments and 3 OTCs per treatment were used. Legume species were very sensitive to O3, because 78% of the tested species showed detrimental effects on their total biomass relative growth rate (RGR) following their exposure to O3. The Trifolium genus was particularly sensitive showing O3-induced adverse effects on most of the assessed parameters. Gramineae plants were less sensitive than Leguminosae species because detrimental effects on total biomass RGR were only observed in 14% of the assessed species. No relationship was found between relative growth rates when growing in clean air and O3 susceptibility. The implications of these effects on the performance of dehesa acidic grasslands and on the definition of ozone critical levels for the protection of semi-natural vegetation are discussed.

Biomaterials from beer manufacture waste for bone growth scaffolds

Agricultural wastes are a source of renewable raw materials (RRM), with structures that can be tailored for the use envisaged. Here, they have proved to be good replacement candidates for use as biomaterials for the growth of osteoblasts in bone replacement therapies. Their preparation is more cost effective than that of materials presently in use with the added bonus of converting a low-cost waste into a value-added product. Due to their origin these solids are ecomaterials. In this study, several techniques, including X-ray diffraction (XRD), chemical analysis, mercury intrusion porosimetry (MIP), scanning electron microscopy (SEM), and bioassays, were used to compare the biocompatibility and cell growth of scaffolds produced from beer bagasse, a waste material from beer production, with a control sample used in bone and dental regenerative processes.

Growth response of broilers to lysine levels and hydrolyzed porcine digestive mucosa (Palbio) inclusion in diet from 1 to 21 d of age

Palbio (PAL, Palbio 50 RD, Bioibérica, Spain) is a protein concentrate based on hydrolyzed porcine digestive mucosa dried under a fluid bed system over a soybean carrier, currently used in piglet feeds. The digestibility of PAL is very high and the product may be an excellent source of protein for young chicks. An experiment was conducted with 1,280 straight-run one-d-old Ross 308 chicks to evaluate the growth response of broilers to dietary inclusion of PAL.

Diffusion of Zn into GaAs and AlGaAs from isothermal Liquid-phase epitaxy solutions

In this work we present results of zinc diffusion in GaAs using the liquid phase epitaxy technique from liquid solutions of Ga‐As‐Zn and Ga‐As‐Al‐Zn. Using silicon‐doped n‐GaAs substrates, working at a diffusion temperature of 850 °C, and introducing a dopant concentration ranging 1018–1019 cm−3, the most important findings regarding the diffusion properties are as follows: (a) zinc concentration in the solid depends on the square root of zinc atomic fraction in the liquid; (b) the diffusion is dominated by the interstitial‐substitutional process; (c) the diffusivity D varies as about C3 in the form D=2.9×10−67C3.05; (d) aluminum plays the role of the catalyst of the diffusion process, if it is introduced in the liquid solution, since it is found that D varies as (γAsXlAs)−1; (e) the zinc interstitial is mainly doubly ionized (Zn++i); (f) the zinc diffusion coefficient in Al0.85 Ga0.15 As is about four times greater than in GaAs; (g) by means of all these results, it is possible to control zinc diffusion processes in order to obtain optimized depth junctions and doping levels in semiconductor device fabrication.

Molecular cloning and characterization of an amidase from Arabidopsis thaliana capable of converting indole-3-acetamide into the plant growth hormone, indole-3-acetic acid

Acylamidohydrolases from higher plants have not been characterized or cloned so far. AtAMI1 is the first member of this enzyme family from a higher plant and was identified in the genome of Arabidopsis thaliana based on sequence homology with the catalytic-domain sequence of bacterial acylamidohydrolases, particularly those that exhibit indole-3-acetamide amidohydrolase activity. AtAMI1 polypeptide and mRNA are present in leaf tissues, as shown by immunoblotting and RT-PCR, respectively. AtAMI1 was expressed from its cDNA in enzymatically active form and exhibits substrate specificity for indole-3-acetamide, but also some activity against l-asparagine. The recombinant enzyme was characterized further. The results show that higher plants have acylamidohydrolases with properties similar to the enzymes of certain plant-associated bacteria such as Agrobacterium-, Pseudomonas- and Rhodococcus-species, in which these enzymes serve to synthesize the plant growth hormone, indole-3-acetic acid, utilized by the bacteria to colonize their host plants. As indole-3-acetamide is a native metabolite in Arabidopsis thaliana, it can no longer be ruled out that one pathway for the biosynthesis of indole-3-acetic acid involves indole-3-acetamide-hydrolysis by AtAMI1.

On the practical uselessness of structural designs derived from some theoretical optimal solutions

A recent study by Pichugin et al. recall the Hemp’s solution for uniform load of 1974, showing that if allowable tensile and compressive stresses are unequal then the Hemp’s arch is optimal provided the ratio of stresses falls within a certain interval. This work is undoubtedly an important pass forward to find an optimal solution for the mathematical problem stated by Hemp. Furthermore, the Authors suggest that their optimal solutions are potentially reasonable from a practical perspective for materials with more allowable compressive stress than tensile one, as this kind of materials used to be not too much expensive. In this paper we profoundly analyse the solutions of the Authors from this practical perspective finding that the original Hemp’s solution —albeit sub-optimal for the mathematical problem— leads to real designs that are more efficient than the theoretic optimal solutions of the Authors.We show that the reasons for this shocking fact has to do with the class of problems considered by Hemp and the Authors.

Influence of energy concentration and feed form of the diet on growth performance and digestive traits of brown egg-laying pullets from 1 to 120 days of age

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Growth data from a field trial of Quercus suber plants regenerated from selected trees and their half-sib progenies by somatic embryogenesis

The development of reliable clonal propagation technologies is a requisite for performing Multi-Varietal Forestry (MVF). Somatic embryogenesis is considered the tissue culture based method more suitable for operational breeding of forest trees. Vegetative propagation is very difficult when tissues are taken from mature donors, making clonal propagation of selected trees almost impossible. We have been able to induce somatic embryogenesis in leaves taken from mature oak trees, including cork oak (Quercus suber). This important species of the Mediterranean ecosystem produces cork regularly, conferring to this species a significant economic value. In a previous paper we reported the establishment of a field trial to compare the growth of plants of somatic origin vs zygotic origin, and somatic plants from mature trees vs somatic plants from juvenile seedlings. For that purpose somatic seedlings were regenerated from five selected cork oak trees and from young plants of their half-sib progenies by somatic embryogenesis. They were planted in the field together with acorn-derived plants of the same families. After the first growth period, seedlings of zygotic origin doubled the height of somatic seedlings, showing somatic plants of adult and juvenile origin similar growth. Here we provide data on height and diameter increases after two additional growth periods. In the second one, growth parameters of zygotic seedlings were also significantly higher than those of somatic ones, but there were not significant differences in height increase between seedlings and somatic plants of mature origin. In the third growth period, height and diameter increases of somatic seedlings cloned from the selected trees did not differ from those of zygotic seedlings, which were still higher than data from plants obtained from somatic embryos from the sexual progeny. Therefore, somatic seedlings from mature origin seem not to be influenced by a possible ageing effect, and plants from somatic embryos tend to minimize the initial advantage of plants from acorns

Effect of solute and matric potential on growth rate of fungal species isolated from cheese

The effect of water potential ( J w ) on the growth of 15 fungal species isolated from cheeses was analysed. The species, identified mainly by analysis of DNA sequences, belonged to genera Penicillium , Geotrichum , Mucor , Aspergillus , Microascus and Talaromyces . Particularly, the effect of matric potential ( J m ), and ionic (NaCl) and non-ionic (glycerol) solute potentials ( J s ) on growth rate was studied. The response of strains was highly dependent on the type of J w . For J s , clear profiles for optimal, permissive and marginal conditions for growth were obtained, and differences in growth rate were achieved comparing NaCl and glycerol for most of the species. Conversely, a sustained growth was obtained for J m in all the strains, with the exception of Aspergillus pseudoglaucus , whose growth increased proportionally to the level of water stress. Our results might help to understand the impact of environmental factors on the ecophysiology and dynamics of fungal populations associated to cheeses.

The effect of a mono component protease and different AMEn levels in broiler diets on growth performance from 1 to 18 days of age.

The objective of the present study was to evaluate the effect of the inclusion of a mono component serine protease (RONOZYME ProAct, DSM Nutritional Products) in diets with two different AMEn contents on apparent ileal digestibility (AID) of amino acids (AA) and growth performance in broilers from 1 to 18 days of age.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

Growth rate and TRI5 gene expression profiles of Fusarium equiseti strains isolated from Spanish cereals cultivated on wheat and barley media at different environmental conditions

Fusarium equiseti is a toxigenic species that often contaminates ce real crops from diverse climatic regions such as Northern and Southern Europe. Previous results suggested the existence of two distinct populations within this species with differences in toxin pro file which largely corresponded to North and South Europe (Spain). In this work, growth rate profiles of 4 F. equiseti strains isolated from different cereals and distinct Spanish regions were determined on wheat and barley based media at a range of temperatures (15, 20, 25, 30, 35 and 40 °C) and water potentialregimens(−0.7,−2.8,−7.0,and −9.8MPa,correspondingto 0.99,0.98,0.95 and 0.93aw values).Growth was observed at all temperatures except at 40 °C, and at all the solute potential values except at−9.8 MPa when combined with 15 °C. Optimal growth was observed at 20– 30 °C and −0.7/−2.8 MPa. The effect of these factors on trichothecene biosynthesis was examined on a F. equiseti strain using a newly developed real time RT-PCR protocol to quantify TRI5 gene expression at 15, 25 and 35 °C and −0.7, −2.8, − 7.0 and −9.8 MPa on wheat and barley based media. Induction of TRI5 expression was detected between 25 and 35 °C and −0.7 and − 2.8 MPa, with maximum values at 35 °C and −2.8 MPa being higher in barley than in wheat medium. These results appeared to be consistent with a population well adapted to the present climatic conditions and predicted scenarios for Southern Europe and suggested some differences depending on the cereal considered. These are also discussed in relation to other Fusarium species co-occurring in cereals grown in this region and to their significance for prediction and control strategies of toxigenic risk in future scenarios of climate change for this region.

Inluence of source and level of glycerin in the diet on growth performance, liver characteristics, and nturient digestibility in broilers from hatching to 21 days of age

The influence of source and level of inclusion of raw glycerin (GLYC) in the diet on growth performance, digestive traits, total tract apparent retention (TTAR), and apparent ileal digestibility of nutrients was studied in broilers from 1 to 21 d of age. There was a control diet based on corn and soybean meal and 8 additional diets that formed a 2 × 4 factorial with 2 sources of GLYC and 4 levels of inclusion (2.5, 5.0, 7.5, and 10%). The GLYC used were obtained from the same original batch of soy oil that was dried under different processing conditions and contained 87.5 or 81.6% glycerol, respectively. Type of processing of the GLYC did not affect any of the variables studied except DM and organic matter retention (P < 0.05) that was higher for the 87.5% glycerol diet. From d 1 to 21, feed conversion ratio (FCR) improved linearly (L, P ≤ 0.01) as the GLYC content of the diet increased, but ADG was not affected. On d 21, the relative weight (% BW) of the liver and the digestive tract increased (L, P < 0.01) as the level of GLYC in the diet increased, but lipid concentration in the liver was not affected. The TTAR of DM and organic matter increased quadratically (Q, P < 0.05) and the AMEn content of the diet increased linearly (L, P < 0.01) with increases in dietary GLYC. Also, the apparent ileal digestibility of DM (L, P < 0.05; Q, P = 0.07) and gross energy (L, P < 0.01) increased as the GLYC content of the diet increased. It is concluded that raw GLYC from the biodiesel industry can be used efficiently, up to 10% of the diet, as a source of energy for broilers from 1 to 21 d of age and that the energy content of well-processed raw GLYC depends primarily on its glycerol content.

Effect of solute and matric potential on growth rate of fungal species isolated from cheese

The effect of water potential ( J w ) on the growth of 15 fungal species isolated from cheeses was analysed. The species, identi fi ed mainly by analysis of DNA sequences, belonged to genera Penicillium, Geotrichum, Mucor , Aspergillus , Microascus and Talaromyces . Particularly, the effect of matric potential ( J m ), and ionic (NaCl) and non-ionic (glycerol) solute potentials ( J s ) on growth rate was studied. The response of strains was highly dependent on the type of J w . For J s, clear profiles for optimal, permissive and marginal conditions for growth were obtained, and differences in growth rate were achieved comparing NaCl and glycerol for most of the species. Conversely, a sustained growth was obtained for J m in all the strains, with the exception of Aspergillus pseudoglaucus, whose growth increased proportionally to the level of water stress. Our results might help to understand the impact of environmental factors on the ecophysiology and dynamics of fungal populations associated to cheeses.