Pré-regulador retificador entrelaçado (Interleaved) ZCS-FM boost, com controle digital através de dispositivo FPGA e linguagem VHDL

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

A novel single-phase ZCS-PWM high power factor boost rectifier

This paper presents a novel single-phase high power factor PWM boost rectifier, featuring soft commutation of the active switches at zero-current (ZCS). It incorporates the most desirable properties of the conventional PWM and the soft-switching resonant techniques. The input current shaping is achieved with average current mode control, and continuous inductor current mode. This new PWM converter provides ZCS turn-on and turn-off of the active switches, and it is suitable for high power applications employing IGBTs. Principle of operation, theoretical analysis, a design example, and experimental results from a laboratory prototype rated at 1600 W with 400 Vdc output voltage are presented. The measured efficiency and power factor were 96.2% and 0.99 respectively, with an input current THD equal to 3.94%, for an input voltage THD equal to 3.8%, at rated load.

Five-level Z-source diode-clamped inverter

This study proposes a five-level Z-source diode-clamped inverter designed with two intermediate Z-source networks connected between the dc input sources and rear-end inverter circuitry. By partially shorting the Z-source networks, new operating states not previously reported for two-level Z-source inverter are introduced here for operating the proposed inverter with voltage buck-boost energy conversion ability and five-level phase voltage switching. These characteristic features are in fact always ensured at the inverter terminal output by simply adopting a properly designed carrier modulation scheme, which always inserts two partial shoot-through states per half carrier cycle for smooth balanced operation. Theoretical findings and practical issues identified are eventually verified by constructing a scaled down laboratory prototype for testing.

Topological design and modulation strategy for buck-boost three-level inverters

To date, designed topologies for DC-AC inversion with both voltage-buck and boost capabilities are mainly focused on two-level circuitries with extensions to three-level possibilities left nearly unexplored. Contributing to this area of research, this paper presents the design of a number of viable buck-boost three-level inverters that can also support bidirectional power conversion. The proposed front-end circuitry is developed from the Cuk-derived buck-boost two-level inverter, and by using the "alternative phase opposition disposition" (APOD) modulation scheme, the buck-boost three-level inverters can perform distinct five-level line voltage and three-level phase voltage switching by simply controlling the active switches located in the designed voltage boost section of the circuits. As a cost saving option, one active switch can further be removed from the voltage-boost section of the circuits by simply re-routing the gating commands of the remaining switches without influencing the ac output voltage amplitude. To verify the validity of the proposed inverters, Matlab/PLECS simulations were performed before a laboratory prototype was implemented for experimental testing.

Topological design and modulation strategy for buck-boost three-level inverters

To date, designed topologies for DC-AC inversion with both voltage buck and boost capabilities are mainly focused on two-level circuitries with extensions to three-level possibilities left nearly unexplored. Contributing to this area of research, this paper presents the design of a number of viable buck-boost three-level inverters that can also support bidirectional power conversion. The proposed front-end circuitry is developed from the Cuk-derived buck-boost two-level inverter, and by using the ldquoalternative phase opposition dispositionrdquo modulation scheme, the buck-boost three-level inverters can perform distinct five-level line voltage and three-level phase voltage switching by simply controlling the active switches located in the designed voltage boost section of the circuits. As a cost saving option, one active switch can further be removed from the voltage boost section of the circuits by simply rerouting the gating commands of the remaining switches without influencing the AC output voltage amplitude. To verify the validity of the proposed inverters, MATLAB/PLECS simulations were performed before a laboratory prototype was implemented for experimental testing.

Investigations of noise and of quantum interference in proximity effect bridges

This work reports investigations upon weakly superconducting proximity effect bridges. These bridges, which exhibit the Josephson effects, are produced by bisecting a superconductor with a short (<1µ) region of material whose superconducting transition temperature is below that of the adjacent superconductors. These bridges are fabricated from layered refractory metal thin films whose transition temperature will depend upon the thickness ratio of the materials involved. The thickness ratio is changed in the area of the bridge to lower its transition temperature. This is done through novel photolithographic techniques described in the text, Chapter 2.

If two such proximity effect bridges are connected in parallel, they form a quantum interferometer. The maximum zero voltage current through this circuit is periodically modulated by the magnetic flux through the circuit. At a constant bias current, the modulation of the critical current produces a modulation in the dc voltage across the bridge. This change in dc voltage has been found to be the result of a change in the internal dissipation in the device. A simple model using lumped circuit theory and treating the bridges as quantum oscillators of frequency ω = 2eV/h, where V is the time average voltage across the device, has been found to adequately describe the observed voltage modulation.

The quantum interferometers have been converted to a galvanometer through the inclusion of an integral thin film current path which couples magnetic flux through the interferometer. Thus a change in signal current produces a change in the voltage across the interferometer at a constant bias current. This work is described in Chapter 3 of the text.

The sensitivity of any device incorporating proximity effect bridges will ultimately be determined by the fluctuations in their electrical parameters. He have measured the spectral power density of the voltage fluctuations in proximity effect bridges using a room temperature electronics and a liquid helium temperature transformer to match the very low (~ 0.1 Ω) impedances characteristic of these devices.

We find the voltage noise to agree quite well with that predicted by phonon noise in the normal conduction through the bridge plus a contribution from the superconducting pair current through the bridge which is proportional to the ratios of this current to the time average voltage across the bridge. The total voltage fluctuations are given by <V^2(f ) > = 4kTR^2_d I/V where R_d is the dynamic resistance, I the total current, and V the voltage across the bridge . An additional noise source appears with a strong 1/f^(n) dependence , 1.5 < n < 2, if the bridges are fabricated upon a glass substrate. This excess noise, attributed to thermodynamic temperature fluctuations in the volume of the bridge, increases dramatically on a glass substrate due to the greatly diminished thermal diffusivity of the glass as compared to sapphire.

高稳定度高压开关电源设计

本文分析了国内外开关电源的发展和现状，研究了高压开关电源的基本原理以及开关电源在电力直流操作电源系统中的应用。根据兰州重离子加速器的要求，设计了一种高稳定度高压开关电源。该系统在借鉴国外和已有的类似电源的基础上，通过采用新的元器件和新的电力电子技术设计而成。该系统以工GBT作为功率开关器件，构成BUCK开关变换器，采用脉宽调制（PWM）技术来控制输出电压的变化。系统中采用TL494、UC3637、ML57962等一系列集成电路，以实现实时采样电压反馈信号、PWM信号以及工GBT所需要的功率驱动信号。电路中采用斩波调压和逆变分开，各司其职的结构，保证了电路可靠、线性的调节；采用前馈电路进行补偿，确保系统能很好的抑制电网的中频扰动。通过MATLAB的计算仿真证明，这些措施都对对系统的性能起到了很好的作用。为了系统的安全可靠，还设计了软启动和过流保护电路。通过实验证明该系统能安全、可靠运行，达到了设计要求。

Analysis of the effect of finite d.c. blocking capacitance and finite d.c. feed inductance on the performance of inverse class-E amplifiers

The first analysis and synthesis equations for the newly introduced inverse Class-E amplifier when operated with a finite d.c. blocking capacitance and a finite d.c.-feed inductance are presented in the paper. Closed-form design equations are derived in order to establish the circuit component values required for optimum synthesis. Excellent agreement between numerical simulation results and theoretical prediction is obtained. It is shown that drain efficiency approaching 100 at a pre-specified output power level can be achieved as zero-current switching and zero-current derivative conditions are simultaneously satisfied. The proposed analysis offers the prospect for realistic MMIC implementation.

Multi-Level Wordline Driver for Low Power SRAMs in Nano-Scale CMOS Technology

In this paper, a multi-level wordline driver scheme is presented to improve SRAM read and write stability while lowering power consumption during hold operation. The proposed circuit applies a shaped wordline voltage pulse during read mode and a boosted wordline pulse during write mode. During read, the applied shaped pulse is tuned at nominal voltage for short period of time, whereas for the remaining access time, the wordline voltage is reduced to a lower level. This pulse results in improved read noise margin without any degradation in access time which is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during hold mode, the wordline voltage starts from a negative value and reaches zero voltage, resulting in a lower leakage current compared to conventional SRAM. Our simulations using TSMC 65nm process show that the proposed wordline driver results in 2X improvement in static read noise margin while the write margin is improved by 3X. In addition, the total leakage of the proposed SRAM is reduced by 10% while the total power is improved by 12% in the worst case scenario of a single SRAM cell. The total area penalty is 10% for a 128Kb standard SRAM array.

Design, implementation and characterisation of a contactless power transfer system for rotating applications

This paper describes the design, implementation and characterisation of a contactless power transfer system for rotating applications. The power transfer system is based upon a zero-voltage-switched, full-bridge, DC-DC converter, but utilises a non-standard transformer. This transformer allows power transfer between its primary and secondary windings while also allowing free rotation between these windings. The aim of this research is to develop a solution that could replace mechanical slip-rings in certain applications where a non-contacting system would be advantageous. Based upon the design method presented in this paper, a 2 kW prototype system is constructed. Results obtained from testing the 2 kW prototype are presented and discussed. This discussion considers how the performance of the transformer varies with rotation and also the overall efficiency of the system

Electronic ballast for multiple fluorescent lamp systems

An electronic ballast for multiple tubular fluorescent lamp systems is presented. The proposed structure has a high value for the power factor, a dimming capability, and soft switching of the semiconductor devices operated at high frequencies. A zero-current switching pulse width modulated SEPIC converter is used as the rectifying stage and it is controlled using the instantaneous average input current technique. The inverting stage consists of classical resonant half-bridge converter with series-resonant parallel-loaded filters. The dimming control technique is based on varying the switching frequency and monitoring the phase shift of the current drained by the filters and lamps in order to establish a closed loop control. Experimental results are presented that validate the theoretical analysis.

Uma aplicacao da celula de comutacao ZVS-PWM-GEPAE ao conversor DC-AC

This work presents the design and procedure of a DC-to-AC converter using a ZVS Commutation Cell developed by Barbi and Martins (1991) and applied to the family of DC-to-DC PWM converters. Firstly, we show the cell applied to buck converter. The stages of operation and the main current and voltage equations of the resonant devices are presented. Next, we adapt the converter to the regenerative operation mode. Hence, the full bridge converter at low frequency operation is conected on the DC-to-DC stage (at high frequency) output ends (Seixas, 1993). Commutation of zero voltage for all switches, PWM at constant frequency and neither overvoltage nor additional current stress are observed by digital simulation. The design example and experimental results obtained by prototype rated at 275 V, 1 kW and 40 kHz are also presented.

Modeling of pre-regulator boost ZCS interleaved operating in critical conduction mode and with high power factor

This paper presents a new pre-regulator boost operating in the boundary area between the continuous and discontinuous conduction modes of the boost inductor current, where the switches and boost diode performing zero-current commutations during its turn-off, eliminating the disadvantages related to the reverse recovery losses and electromagnetic interference problems of the boost diode when operating in the continuous conduction mode. Additionally, the interleaving technique is applied in the power cell, providing a significant input current ripple reduction. It should be noticed that the main objective of this paper is to present a complete modeling for the converter operating in the critical conduction mode, allowing an improved design procedure for interleaved techniques with high input power factor, a complete dynamic analysis of the structure, and the possibility of implementing digital control techniques in closed loop.

Dimmable electronic ballast with high power-factor SEPIC preregulator, for multiple tubular fluorescent lamps

An electronic ballast for multiple tubular fluorescent lamps is presented in this paper. The proposed structure features high power-factor, dimming capability, and soft-switching to the semiconductor devices operated in high frequencies. A Zero-Current-Switching - Pulse-Width-Modulated (ZCS-PWM) SEPIC converter composes the rectifying stage, controlled by the instantaneous average input current technique, performing soft-commutations and high input power factor. Regarding the inverting stage, it is composed by a classical resonant Half-Bridge converter, associated to Series Parallel-Loaded Resonant (SPLR) filters. The dimming control technique employed in this Half-Bridge inverter is based on the phase-shift in the current processed through the sets of filter + lamp. In addition, experimental results are shown in order to validate the developed analysis.

Construção de uma junção Josephson em filmes finos supercondutores do sistema Bi1.8Pb0.4Sr2CaCu2Ox tratados termicamente em um forno microondas doméstico

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)