170 resultados para layouts


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Topology optimization methods have been shown to have extensive application in the design of microsystems. However, their utility in practical situations is restricted to predominantly planar configurations due to the limitations of most microfabrication techniques in realizing structures with arbitrary topologies in the direction perpendicular to the substrate. This study addresses the problem of synthesizing optimal topologies in the out-of-plane direction while obeying the constraints imposed by surface micromachining. A new formulation that achieves this by defining a design space that implicitly obeys the manufacturing constraints with a continuous design parameterization is presented in this paper. This is in contrast to including manufacturing cost in the objective function or constraints. The resulting solutions of the new formulation obtained with gradient-based optimization directly provide the photolithographic mask layouts. Two examples that illustrate the approach for the case of stiff structures are included.

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Spectral efficiency is a key characteristic of cellular communications systems, as it quantifies how well the scarce spectrum resource is utilized. It is influenced by the scheduling algorithm as well as the signal and interference statistics, which, in turn, depend on the propagation characteristics. In this paper we derive analytical expressions for the short-term and long-term channel-averaged spectral efficiencies of the round robin, greedy Max-SINR, and proportional fair schedulers, which are popular and cover a wide range of system performance and fairness trade-offs. A unified spectral efficiency analysis is developed to highlight the differences among these schedulers. The analysis is different from previous work in the literature in the following aspects: (i) it does not assume the co-channel interferers to be identically distributed, as is typical in realistic cellular layouts, (ii) it avoids the loose spectral efficiency bounds used in the literature, which only considered the worst case and best case locations of identical co-channel interferers, (iii) it explicitly includes the effect of multi-tier interferers in the cellular layout and uses a more accurate model for handling the total co-channel interference, and (iv) it captures the impact of using small modulation constellation sizes, which are typical of cellular standards. The analytical results are verified using extensive Monte Carlo simulations.

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Large software systems are developed by composing multiple programs. If the programs manip-ulate and exchange complex data, such as network packets or files, it is essential to establish that they follow compatible data formats. Most of the complexity of data formats is associated with the headers. In this paper, we address compatibility of programs operating over headers of network packets, files, images, etc. As format specifications are rarely available, we infer the format associated with headers by a program as a set of guarded layouts. In terms of these formats, we define and check compatibility of (a) producer-consumer programs and (b) different versions of producer (or consumer) programs. A compatible producer-consumer pair is free of type mismatches and logical incompatibilities such as the consumer rejecting valid outputs gen-erated by the producer. A backward compatible producer (resp. consumer) is guaranteed to be compatible with consumers (resp. producers) that were compatible with its older version. With our prototype tool, we identified 5 known bugs and 1 potential bug in (a) sender-receiver modules of Linux network drivers of 3 vendors and (b) different versions of a TIFF image library.

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Poly(dimethylsiloxane) (PDMS) is usually considered as a dielectric material and the PDMS microchannel wall can be treated as an electrically insulated boundary in an applied electric field. However, in certain layouts of microfluidic networks, electrical leakage through the PDMS microfluidic channel walls may not be negligible, which must be carefully considered in the microfluidic circuit design. In this paper, we report on the experimental characterization of the electrical leakage current through PDMS microfluidic channel walls of different configurations. Our numerical and experimental studies indicate that for tens of microns thick PDMS channel walls, electrical leakage through the PDMS wall could significantly alter the electrical field in the main channel. We further show that we can use the electrical leakage through the PDMS microfluidic channel wall to control the electrolyte flow inside the microfluidic channel and manipulate the particle motion inside the microfluidic channel. More specifically, we can trap individual particles at different locations inside the microfluidic channel by balancing the electroosmotic flow and the electrophoretic migration of the particle.

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Os passageiros têm reclamado da diminuição do conforto na classe econômica dos aviões comerciais. A autoridade aeronáutica brasileira instituiu um selo de qualidade, mas as empresas aéreas brasileiras mantêm os mesmos arranjos internos em seus aviões. Estadissertaçãotrata da avaliação do espaço entre as poltronas e a sua influência no conforto dos passageiros em vôos comerciais. Realizaram-se avaliações da usabilidade utilizando-se um simulador de cabine para treinamento de tripulantes e um avião B737-300. Os resultados indicam uma forte relação entre os níveis de conforto e o passo (medida de repetição das fileiras de poltronas ao longo do avião).

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A detailed study of the design issues relevant to long-wavelength monolithic mode-locked lasers is presented. Following a detailed review of the field, we have devised a validated travelling wave model to explore the limits of mode-locking in monolithic laser diodes, not only in terms of pulse duration and repetition rate, but also in terms of stability. It is shown that fast absorber recovery is crucial for short pulse width, that the ratio of gain to absorption saturation is key in accessing ultrashort pulses and that low alpha factors give only modest benefit. Finally, optimized contact layouts are shown to greatly enhance pulse stability and the overall operational success. The design rules show high levels of consistency with published experimental data.

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A host of methods and tools to support designing are being developed in Cambridge EDC. These range from tools for design management to those for the generation and selection of design ideas, layouts, materials and production processes. A project, to develop a device to improve arm mobility of muscular dystrophy sufferers, is undertaken as a test-bed to evaluate and improve these methods and tools as well as to observe and modify its design and management processes. This paper presents the difficulties and advantages of using design methods and tools within this rehabilitation design context, with special focus on the evolution of the designs, tools, and management processes.

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This paper investigates the possibility of improving the performance of railway vehicle suspensions by incorporating a newly developed mechanical device known as the inerter. A comparative study of several low-complexity passive suspension layouts is made. Improved performance for the lateral and vertical ride comfort, as well as lateral body movement when curving are demonstrated in comparison with the conventional suspension layout. The constraints imposed are to maintain the same level of other performance metrics. The calculations and optimisations are based on linearised plan-view and side-view high-speed train mathematical models. © 2012 Copyright Taylor and Francis Group, LLC.

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Multimode polymer waveguides are promising for use in board-level optical interconnects. In recent years, various on-board optical interconnection architectures have been demonstrated making use of passive routing waveguide components. In particular, 90° bends have played important roles in complex waveguide layouts enabling interconnection between non co-linear points on a board. Due to the dimensions and index step of the waveguides typically used in on-board optical interconnects, low-loss bends are typically limited to a radius of ∼ 10 mm. This paper therefore presents the design and fabrication of compact low-loss waveguide bends with reduced radii of curvature, offering significant reductions in the required areas for on-board optical circuits. The proposed design relies on the exposure of the bend section to the air, achieving tighter light confinement along the bend and reduced bending losses. Simulation studies carried out with ray tracing tools and experimental results from polymer samples fabricated on FR4 are presented. Low bending losses are achieved from the air-exposed bends up to 4 mm of radius of curvature, while an improvement of 14 μm in the 1 dB alignment tolerances at the input of these devices (fibre to waveguide coupling) is also obtained. Finally, the air-exposed bends are employed in an optical bus structure, offering reductions in insertion loss of up to 3.8 dB. © 2013 IEEE.

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Mechanical spring-damper network performance can often be improved by the inclusion of a third passive component called the inerter. This ideally has the characteristic that the force at the terminals is directly proportional to the relative acceleration between them. The fluid inerter presented here has advantages over mechanical ball screw devices in terms of simplicity of design. Furthermore, it can be readily adapted to implement various passive network layouts. Variable orifices and valves can be included to provide series or parallel damping. Test data from prototypes with helical tubes have been compared with models to investigate parasitic damping effects of the fluid. © 2013 Copyright Taylor and Francis Group, LLC.

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The aim of the present study was to investigate whether people can establish two oblique spatial reference directions to represent objects’ locations in memory. Participants learned a layout of objects from two oblique viewpoints (0º and 225º) and made judgments of relative direction (“Imagine you are standing at X, facing Y, please point to Z”). Experiments 1 to 3 showed that performance in pointing were better at either one of the familiar imagined headings (0º and 225º) in most of the participants even when they were instructed to learn the layout along their actual heading at both learning directions, and when their actual headings at the test were the same as the imagined headings. Experiments 4 to 6 showed performance in pointing could be equivalent at the two familiar imagined headings for significant number of the participants when participants learned two different set of objects occupied at the same locations from the two learning viewpoints, and when participants learned the same layout of objects together with two different layouts from the two learning viewpoints. These results suggest that the orientation dependent performance in Experiments 1 to 3 cannot be attributed to the possibility that participants had formed two oblique spatial reference directions during learning but only used one of them during testing. Experiments 7 and 8 further showed that the performance of pointing at the two familiar viewpoints were significantly different when participants experienced one viewpoint by learning the actual layout and the other viewpoint by learning the map of the same layout, and when participants experienced two viewpoints alternatively over the ten times of learning sessions. All these results strongly suggest that people establish only one spatial reference system to represent locations of objects when they learn the same layout in the same background from two oblique viewpoints.

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We describe a heuristic method for drawing graphs which uses a multilevel technique combined with a force-directed placement algorithm. The multilevel process groups vertices to form clusters, uses the clusters to define a new graph and is repeated until the graph size falls below some threshold. The coarsest graph is then given an initial layout and the layout is successively refined on all the graphs starting with the coarsest and ending with the original. In this way the multilevel algorithm both accelerates and gives a more global quality to the force- directed placement. The algorithm can compute both 2 & 3 dimensional layouts and we demonstrate it on a number of examples ranging from 500 to 225,000 vertices. It is also very fast and can compute a 2D layout of a sparse graph in around 30 seconds for a 10,000 vertex graph to around 10 minutes for the largest graph. This is an order of magnitude faster than recent implementations of force-directed placement algorithms.

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Very Large Transport Aircraft (VLTA) pose considerable challenges to designers, operators and certification authorities. Questions concerning seating arrangement, nature and design of recreational space, the number, design and location of internal staircases, the number of cabin crew required and the nature of the cabin crew emergency procedures are just some of the issues that need to be addressed. Other more radical concepts such as blended wing body (BWB) design, involving one or two decks with possibly four or more aisles offer even greater challenges. Can the largest exits currently available cope with passenger flow arising from four or five aisles? Do we need to consider new concepts in exit design? Should the main aisles be made wider to accommodate more passengers? In this paper we demonstrate how computer based evacuation models can be used to investigate these issues through examination of staircase evacuation procedures for VLTA and aisle/exit configuration for BWB cabin layouts.

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Computer based mathematical models describing the aircraft evacuation process have a vital role to play in the design and development of safer aircraft, the implementation of safer and more rigorous certification criteria, in cabin crew training and post-mortem accident investigation. As the risk of personal injury and the costs involved in performing full-scale certification trials are high, the development and use of these evacuation modelling tools are essential. Furthermore, evacuation models provide insight into the evacuation process that is impossible to derive from a single certification trial. The airEXODUS evacuation model has been under development since 1989 with support from the UK CAA and the aviation industry. In addition to describing the capabilities of the airEXODUS evacuation model, this paper describes the findings of a recent CAA project aimed at investigating model accuracy in predicting past certification trials. Furthermore, airEXODUS is used to examine issues related to the Blended Wing Body (BWB) and Very Large Transport Aircraft (VLTA). These radical new aircraft concepts pose considerable challenges to designers, operators and certification authorities. BWB concepts involving one or two decks with possibly four or more aisles offer even greater challenges. Can the largest exits currently available cope with passenger flow arising from four or five aisles? Do we need to consider new concepts in exit design? Should the main aisle be made wider to accommodate more passengers? In this paper we discuss various issues evacuation related issues associated VLTA and BWB aircraft and demonstrate how computer based evacuation models can be used to investigage these issues through examination of aisle/exit configurations for BWB cabin layouts.

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We describe a heuristic method for drawing graphs which uses a multilevel framework combined with a force-directed placement algorithm. The multilevel technique matches and coalesces pairs of adjacent vertices to define a new graph and is repeated recursively to create a hierarchy of increasingly coarse graphs, G0, G1, …, GL. The coarsest graph, GL, is then given an initial layout and the layout is refined and extended to all the graphs starting with the coarsest and ending with the original. At each successive change of level, l, the initial layout for Gl is taken from its coarser and smaller child graph, Gl+1, and refined using force-directed placement. In this way the multilevel framework both accelerates and appears to give a more global quality to the drawing. The algorithm can compute both 2 & 3 dimensional layouts and we demonstrate it on examples ranging in size from 10 to 225,000 vertices. It is also very fast and can compute a 2D layout of a sparse graph in around 12 seconds for a 10,000 vertex graph to around 5-7 minutes for the largest graphs. This is an order of magnitude faster than recent implementations of force-directed placement algorithms.